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rev 0.4 9/12 copyright ? 2012 by silicon laboratories sim3l1xx this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. sim3l1xx high-performance, low-power, 32-bit precision32? mcu family with up to 256 kb of flash 32-bit arm cortex-m3 cpu - 50 mhz maximum frequency - single-cycle multiplication, hardware division support - nested vectored interrupt control (nvic) with 8 priority levels memory - 32?256 kb flash, in-system programmable - 8?32 kb sram with configurable low power retention clock sources - internal oscillator with pll: 23?50 mhz - low power internal oscillator: 20 mhz - low frequency internal oscillator (lfo): 16.4 khz - external real-time clock (rtc) crystal oscillator - external oscillator: crystal, rc, c, cmos clock power management - three adjustable low drop-out (ldo) regulators - power-on reset circuit and brownout detectors - dc-dc buck converter allows dynamic voltage scaling for maximum efficiency (250 mw output) - multiple power modes supported for low power optimization low power features - 50 na current mode with voltage supply monitor enabled - low-current rtc (180 na from lfo, 300 na from crystal) - 4 s wakeup, register state retention and no reset required from lowest power mode - 175 a/mhz at 3.6 v executing from flash - 140 a/mhz at 3.6 v executing from sram - specialized on-chip charge pum p reduces power consumption - process/voltage/temperature (pvt) monitor 5 v tolerant flexible i/o - up to 62 contiguous 5 v tolerant gpio with one priority cross - bar providing flexibility in pin assignments temperature range: ?40 to +85 c supply voltage: 1.8 to 3.8 v analog peripherals - 12-bit analog-to-digital converter: up to 250 ksps 12-bit mode or 1 msps 10-bit mode - 10-bit current-mode digital-to-analog converter - 2 x low-current comparators digital and communication peripherals - 1 x usart with irda and iso7816 smartcard support - 1 x uart that operates in low power mode - 2 x spis, 1 x i2c, 16/32-bit crc - 128/192/256-bit hardware aes encryption - encoder/decoder: manchester and three-out-ofsix - integrated lcd controller: up to 160 segments (40x4), auto- contrast and low power operation timers/counters - 3 x 32-bit or 6 x 16-bit timers with capture/compare - 16-bit, 6-channel counter with capture/compare/pwm and dead-time controller with differential outputs - 16-bit low power timer/advanced c apture counter operational in the lowest power mode - 32-bit real time clock (rtc) with multiple alarms - watchdog timer - low power mode advanced capture counter (acctr) data transfer peripherals - 10-channel dma controller - 3 channel data transfer manager manages complex dma transfers without core intervention on-chip debugging - serial wire debug (swd) with seri al wire viewer (swv) or jtag (no boundary scan) allow debug and programming - cortex-m3 embedded trace macrocell (etm) package options - qfn options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm) - tqfp options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm) - tfbga option: 80-ball (5.5 x 5.5 mm) arm cortex m3 (50 mhz) 32/64/128/256 kb flash 8/16/32 kb retention ram watchdog supply monitor core / memory / support serial wire or jtag debug / programming + etm clocking / oscillators 50 mhz pll 16 khz low frequency oscillator 20 mhz low power oscillator real-time clock w/ dedicated crystal oscillator external clock (xtal / rc / c / cmos) clock selection and gating 10-ch dma controller + 3x data transfer mgr. analog peripherals sar adc (12-bit 250 ksps / 10-bit 1 msps) current-source dac 2 x low current comparators digital peripherals 1 x uart, 1 x usart w/ irda/smartcard 1 x i2c 2 x spi 3 x 32-bit timers (6 x 16-bit) 6-channel pwm voltage reference flexible pin muxing priority crossbar encoder 62 multi-function 5v-tolerant i/o pins power scalable analog ldo dc-dc buck converter power management unit low power mode charge pump aes crc encoder/decoder low-power timer advanced capture counter scalable digital ldo scalable memory ldo lcd controller www.datasheet.net/ datasheet pdf - http://www..co.kr/
2 rev 0.4 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 3 table of contents 1. related documents and conventions . ................. ................ ................. ................ ............5 1.1. related documents........ ................ ................ ................. ................ ................. ..............5 1.1.1. sim3l1xx reference manual... ................. ................ ................. ................ ............5 1.1.2. hardware access layer (hal) api description .............. .............. .............. ..........5 1.1.3. arm cortex-m3 reference man ual................. .............. .............. .............. ............5 1.2. conventions ................ ................. ................ ................ ................. ................ .............. ...5 2. typical connection diagrams .......... .............. .............. .............. .............. .............. ............6 2.1. power ............... ................ ................ .............. .............. ............... .............. .............. .......6 3. electrical specifications............... ................ .............. .............. ............... .............. ............ ..8 3.1. electrical characteristics ......... ................ ................. .............. .............. .............. ............8 3.2. thermal conditions ........ ................ ................ ................. ................ ................. ............ 28 3.3. absolute maximum rating s.............. ................. ................ ................. ................ ..........29 4. precision32? sim3l1xx system ov erview.......... ................ ................. ................ ..........30 4.1. power ............... ................ ................ .............. .............. ............... .............. .............. ..... 32 4.1.1. dc-dc buck converter (dcdc0). ................ ................. .............. .............. .......... 32 4.1.2. three low dropout ldo regula tors (ldo0) ........... ................. ................ .......... 33 4.1.3. voltage supply monito r (vmon0) ............ ................ ................. ................ .......... 33 4.1.4. power management unit (pmu).......... .............. .............. .............. .............. ........ 33 4.1.5. device power modes............. ................ ................. ................ ................. ............ 33 4.1.6. process/voltage/temperat ure monitor (timer2 and pvtosc 0)............. .......... 36 4.2. i/o.................. ................. ................ .............. .............. .............. .............. ............. ......... 37 4.2.1. general features....... ................. ................ ................ ................. .............. ..........37 4.2.2. crossbar ................ ................ ................ ................. ................ ................. ............ 37 4.3. clocking............ ................ ................ .............. .............. ............... .............. .............. ..... 38 4.3.1. pll (pll0)............... ................ ................. ................ ................. ................ .......... 39 4.3.2. low power oscillator (lposc 0) .............. ................ ................. ................ .......... 39 4.3.3. low frequency oscillator (lfosc 0)............... .............. .............. .............. .......... 39 4.3.4. external oscillators (extosc0 )............... ................ ................. ................ .......... 39 4.4. integrated lcd controller (lcd0).............. .............. .............. .............. .............. .......... 40 4.5. data peripherals.......... ................. ................ ................ ................. ................ ............... 41 4.5.1. 10-channel dma c ontroller............... .............. .............. .............. .............. .......... 41 4.5.2. data transfer m anagers (dtm0, dtm1, dtm2) ............. .............. .............. ........ 41 4.5.3. 128/192/256-bit hardware aes encryption (aes0) ............... ................. ............ 41 4.5.4. 16/32-bit enhanced crc (ecrc0) ............ ................ ................. .............. ..........42 4.5.5. encoder / decoder (encdec0) . ................ ................ ................. .............. .......... 42 4.6. counters/timers.......... ................. ................ ................ ................. ................ ............... 4 3 4.6.1. 32-bit timer (timer0, timer1 , timer2).............. ................ ................. ............ 43 4.6.2. enhanced programmable coun ter array (epca0) ... ................ ................ .......... 43 4.6.3. real-time clock (rtc0) ......... ................. ................ ................. ................ .......... 44 4.6.4. low power timer (lptimer0)... ................ ................ ................. .............. ..........44 4.6.5. watchdog timer (wdtimer0)..... ................ ................. .............. .............. ..........44 4.6.6. low power mode advanced capture counter (acc tr0)........... .............. .......... 45 4.7. communications peripherals ....... .............. .............. .............. .............. .............. .......... 46 4.7.1. usart (usart0) ........ ................ ................ ................. .............. .............. .......... 46 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 4 rev 0.4 4.7.2. uart (uart0).......... ................. ................ ................ ................. .............. .......... 46 4.7.3. spi (spi0, spi1) ...... ................ ................. ................ ................. ................ .......... 47 4.7.4. i2c (i2c0) .............. ................ ................ ................. ................ ................. ............ 47 4.8. analog .............. ................ ................ .............. .............. ............... .............. .............. ..... 48 4.8.1. 12-bit analog-to-digital c onverter (saradc0)...... ................ ................. ............ 48 4.8.2. 10-bit digital-to-analog conver ter (idac0) ............ ................ ................. ............ 48 4.8.3. low current comparators (c mp0, cmp1) ............. ................ ................. ............ 48 4.9. reset sources............. ................. ................ ................ ................. ................ ............... 49 4.10.security ............ ................ ................ .............. .............. ............... .............. ............. ...... 50 4.11.on-chip debugging .... ................. .............. .............. .............. .............. .............. .......... 50 5. ordering information ........ ................. ................ ................ ................. ................ ............... 51 6. pin definitions............ ................. ................ ................ ................. ................ ................ ...... 53 6.1. sim3l1x7 pin definitions . ................ ................. ................ ................. ................ .......... 53 6.2. sim3l1x6 pin definitions . ................ ................. ................ ................. ................ .......... 61 6.3. sim3l1x4 pin definitions . ................ ................. ................ ................. ................ .......... 68 6.4. tqfp-80 package specifications .... ................. ................ ................. ................ .......... 73 6.4.1. tqfp-80 solder mask design. ................. ................ ................. ................ .......... 76 6.4.2. tqfp-80 stencil design ........ ................ ................. ................ ................. ............ 76 6.4.3. tqfp-80 card assembly......... ................. ................ ................. ................ .......... 76 6.5. tfbga-80 package specif ications .............. .............. .............. .............. .............. ........ 77 6.5.1. tfbga-80 solder mask design .. ............... ................ ................. .............. .......... 80 6.5.2. tfbga-80 stencil design........ ................. ................ ................. ................ .......... 80 6.5.3. tfbga-80 card assembly ...... ................. ................ ................. ................ .......... 80 6.6. qfn-64 package specifications .... ................ ................. ................ ................. ............ 81 6.6.1. qfn-64 solder mask design... ................. ................ ................. ................ .......... 83 6.6.2. qfn-64 stencil design ........ .............. .............. .............. .............. .............. .......... 83 6.6.3. qfn-64 card assembly ................ ................ ................. .............. .............. .......... 83 6.7. tqfp-64 package specifications .... ................. ................ ................. ................ .......... 84 6.7.1. tqfp-64 solder mask design. ................. ................ ................. ................ .......... 87 6.7.2. tqfp-64 stencil design ........ ................ ................. ................ ................. ............ 87 6.7.3. tqfp-64 card assembly......... ................. ................ ................. ................ .......... 87 6.8. qfn-40 package specifications .... ................ ................. ................ ................. ............ 88 6.8.1. qfn-40 solder mask design... ................. ................ ................. ................ .......... 90 6.8.2. qfn-40 stencil design ........ .............. .............. .............. .............. .............. .......... 90 6.8.3. qfn-40 card assembly ................ ................ ................. .............. .............. .......... 90 7. revision specific behavior............ ................. .............. .............. .............. .............. .......... 91 7.1. revision identification .... ................ ................ ................. ................ ................. ............ 91 contact information ........... ................ ................ ................. ................ ................. ............... .... 94 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 5 1. related documents and conventions 1.1. related documents this data sheet accompanies several documents to provide the complete description of the sim3l1xx devices. 1.1.1. sim3l1xx reference manual the silicon laboratories sim3lxxx refer ence manual provides the detailed de scription for each peripheral on the sim3l1xx devices. 1.1.2. hardware access layer (hal) api description the silicon laboratories ha rdware access layer (hal) api provides c-language functions to modify and read each bit in the sim3l1xx devices. this description can be found in the sim3xxxx hal api reference manual. 1.1.3. arm cortex-m3 reference manual the arm-specific features like the nested vector inte rrupt controller are described in the arm cortex-m3 reference documentation. the online reference manual can be found here: ? http://infocenter.arm.com/help/ topic/com.arm.doc.subset.cor texm.m3/index.html#cortexm3 . 1.2. conventions the block diagrams in this document use the following formatting conventions: figure 1.1. block diagram conventions internal module external memory block output_pin external to mcu block input_pin internal_output_signal internal_input_signal regn_name / bit_name dma block memory block other internal peripheral block functional block www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 6 rev 0.4 2. typical connection diagrams this section provides typical conn ection diagrams for sim3l1xx devices. 2.1. power figure 2.1 shows a typical connection diagram for the pow er pins of the sim3l1xx devices when the dc-dc buck converter is not used. figure 2.1. connection diagram with dc-dc converter unused figure 2.2 shows a typical connection diagram for the powe r pins of the sim3l1xx devices when the internal dc-dc buck converter is in use and i/o are powered directly from the battery. figure 2.2. connection diagram with dc-dc converter used and i/o powered from battery figure 2.3 shows a typical connection diagram for the power pins of the sim3l1xx devices when used with an external radio device like the silicon labs ezradio ? or ezradiopro ? devices. sim3l1xx device vdc ind vbat/vbatdc vssdc vss dc-dc converter vdrv low dropout regulator (ldo0) viorf vio vlcd 1 uf and 0.1 uf bypass capacitors required for each power pin placed as close to the pins as possible. 10 uf capacitor required on the vlcd pin sim3l1xx device vdc ind vbat/vbatdc vssdc vss dc-dc converter vdrv low dropout regulator (ldo0) to external circuitry viorf vio vlcd 1 uf and 0.1 uf bypass capacitors required for each power pin placed as close to the pins as possible. 4.7, 0.1, and 0.01 uf bypass capacitors required on vbat/vbatdc input 10 uf capacitor required on the vlcd pin 2.2, 0.1, and 0.01 uf bypass capacitors required on vdc output 0.56 uh inductor required between the ind and vdc pins www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 7 figure 2.3. connection diagram with external radio device figure 2.4 shows a typical connection diagram for the pow er pins of the sim3l1xx devices when the dc-dc buck converter is used and the i/o are powered separately. figure 2.4. connection diagram with dc-dc converter used and i/o powered separately sim3l1xx device vdc ind vbat/vbatdc vssdc vss dc-dc converter vdrv low dropout regulator (ldo0) to external radio viorf vlcd capacitors must be placed as close to the pins as possible. 4.7, 0.1, and 0.01 uf bypass capacitors required on vbat/vbatdc input 10 uf capacitor required on the vlcd pin 2.2, 0.1, and 0.01 uf bypass capacitors required on vdc output 0.56 uh inductor required between the ind and vdc pins 1 uf and 0.1 uf bypass capacitors required for each i/o power pin vio sim3l1xx device vdc ind vbat/vbatdc vssdc vss dc-dc converter vdrv low dropout regulator (ldo0) to external circuitry viorf vio vlcd capacitors must be placed as close to the pins as possible. 4.7, 0.1, and 0.01 uf bypass capacitors required on vbat/vbatdc input 10 uf capacitor required on the vlcd pin 2.2, 0.1, and 0.01 uf bypass capacitors required on vdc output 0.56 uh inductor required between the ind and vdc pins 1.8-vbat v 1.8-vbat v 1 uf and 0.1 uf bypass capacitors required for each i/o power pin www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 8 rev 0.4 3. electrical specifications 3.1. electrical characteristics all electrical parameters in all tables are specified under the conditions listed in table 3.1, unless stated otherwise. table 3.1. recommended operating conditions parameter symbol condition min typ max unit operating supply voltage on ? vbat/vbatdc v bat 1.8 ? 3.8 v operating supply voltage on vdc v dc 1.25 ? 3.8 v operating supply voltage on vdrv v drv 1.25 ? 3.8 v operating supply voltage on vio v io 1.8 ? v bat v operation supply voltage on viorf v iorf 1.8 ? v bat v operation supply voltage on vlcd v lcd 1.8 ? 3.8 v system clock frequency (ahb) f ahb 0 ? 50 mhz peripheral clock frequency (apb) f apb 0 ? 50 mhz operating ambient temperature t a ?40 ? +85 c operating junction temperature t j ?40 ? 105 c note: all voltages with respect to v ss . www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 9 table 3.2. power consumption parameter symbol condition min typ max unit digital core supply current normal mode 1 , 2 , 3 , 4 ?full speed with code executing from flash, peripheral clocks on i bat f ahb = 49 mhz, f apb = 24.5 mhz ? 17.5 tbd ma f ahb = 20 mhz, f apb = 10 mhz ? 6.7 tbd ma f ahb = 2.5 mhz, f apb = 1.25 mhz ? 1.15 tbd ma normal mode 1 , 2 , 3 , 4 ?full speed with code executing from flash, peripheral clocks off i bat f ahb = 49 mhz, f apb = 24.5 mhz ? 13.3 tbd ma f ahb = 20 mhz, f apb = 10 mhz ? 5.4 tbd ma f ahb = 2.5 mhz, f apb = 1.25 mhz ? 980 tbd a normal mode 1 , 2 , 3 , 4 ?full speed with code executing from flash, ldos powered by dc-dc, peripheral clocks off i bat f ahb = 49 mhz, f apb = 24.5 mhz v bat = 3.3 v ? 9.7 tbd ma f ahb = 49 mhz, f apb = 24.5 mhz v bat = 3.8 v ? 8.65 tbd ma f ahb = 20 mhz, f apb = 10 mhz v bat = 3.3 v ? 4.15 tbd ma f ahb = 20 mhz, f apb = 10 mhz v bat = 3.8 v ? 3.9 tbd ma power mode 1 1 , 2 , 3 , 4 ?full speed with code executing from ram, peripheral clocks on i bat f ahb = 49 mhz, f apb = 24.5 mhz ? 13.4 tbd ma f ahb = 20 mhz, f apb = 10 mhz ? 4.7 tbd ma f ahb = 2.5 mhz, f apb = 1.25 mhz ? 810 tbd a notes: 1. currents are additive. for example, where i bat is specified and the mode is not mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 2. i ncludes all peripherals that cannot have clocks gated in the clock control module. 3. includes ldo and pll0osc (>20 mhz) or lposc0 ( < 20 mhz) supply current 4. internal digital and memory ldos scaled to optimal output voltage. 5. includes lfo supply current. 6. lcd0 current does not include switching currents for external load. 7. idac output current not included. 8. does not include lc tank circuit. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 10 rev 0.4 power mode 1 1 , 2 , 3 , 4 ?full speed with code executing from ram, peripheral clocks off i bat f ahb = 49 mhz, f apb = 24.5 mhz ? 9.4 tbd ma f ahb = 20 mhz, f apb = 10 mhz ? 3.3 tbd ma f ahb = 2.5 mhz, f apb = 1.25 mhz ? 630 tbd a power mode 1 1 , 2 , 3 , 4 ?full speed with code executing from ram, ldos powered by dc-dc, peripheral clocks off i bat f ahb = 49 mhz, f apb = 24.5 mhz v bat = 3.3 v ? 7.05 tbd ma f ahb = 49 mhz, f apb = 24.5 mhz v bat = 3.8 v ? 6.3 tbd ma f ahb = 20 mhz, f apb = 10 mhz v bat = 3.3 v ? 2.75 tbd ma f ahb = 20 mhz, f apb = 10 mhz v bat = 3.8 v ? 2.6 tbd ma power mode 2 1 , 2 , 3 , 4 ?core halted with peripheral clocks on i bat f ahb = 49 mhz, f apb = 24.5 mhz ? 7.6 tbd ma f ahb = 20 mhz, f apb = 10 mhz ? 2.75 tbd ma f ahb = 2.5 mhz, f apb = 1.25 mhz ? 575 tbd a power mode 2 1 , 2 , 3 , 4 ?core halted with only port i/o clocks on (wake from pin). i bat f ahb = 49 mhz, f apb = 24.5 mhz ? 4 tbd ma f ahb = 20 mhz, f apb = 10 mhz ? 1.47 tbd ma f ahb = 2.5 mhz, f apb = 1.25 mhz ? 430 tbd a power mode 3 1 , 2 ?fast-wake mode (pm3clken = 1) i bat v bat = 1.8 v ? 225 tbd a v bat = 3.8 v ? 320 tbd a table 3.2. power consumption (continued) parameter symbol condition min typ max unit notes: 1. currents are additive. for example, where i bat is specified and the mode is not mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 2. i ncludes all peripherals that cannot have clocks gated in the clock control module. 3. includes ldo and pll0osc (>20 mhz) or lposc0 (< 20 mhz) supply current 4. internal digital and memory ldos scaled to optimal output voltage. 5. includes lfo supply current. 6. lcd0 current does not include switching currents for external load. 7. idac output current not included. 8. does not include lc tank circuit. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 11 power mode 4 1 , 2 , 4 , 5 ?slower clock speed with code executing from flash, peripheral clocks on i bat f ahb = f apb = 16 khz, v bat = 1.8 v ? 330 tbd a f ahb = f apb = 16 khz, v bat = 3.8 v ? 385 tbd a power mode 5 1 , 2 , 4 , 5 ?slower clock speed with code executing from ram, peripheral clocks on i bat f ahb = f apb = 16 khz, v bat = 1.8 v ? 275 tbd a f ahb = f apb = 16 khz, v bat = 3.8 v ? 320 tbd a power mode 6 1 , 2 , 4 , 5 ?core halted with peripheral clocks on i bat f ahb = f apb = 16 khz, v bat = 1.8 v ? 270 tbd a f ahb = f apb = 16 khz, v bat = 3.8 v ? 315 tbd a power mode 8 1 , 2 ?low power sleep, powered through vbat, vio, and viorf at 2.4 v, 32kb of retention ram i bat rtc disabled, t a = 25 c ? 75 tbd na rtc w/ 16.4 khz lfo, t a = 25 c ? 360 tbd na rtc w/ 32.768 khz crystal, t a = 25 c ? 670 tbd na power mode 8 1 , 2 ?low power sleep, powered by the low power mode charge pump, 32kb of reten - tion ram i bat rtc w/ 16.4 khz lfo, v bat = 2.4 v, t a = 25 c ? 180 tbd na rtc w/ 32.768 khz crystal, v bat = 2.4 v, t a = 25 c ? 300 tbd na rtc w/ 16.4 khz lfo, v bat = 3.6 v, t a = 25 c ? 245 tbd na rtc w/ 32.768 khz crystal, v bat = 3.6 v, t a = 25 c ? 390 tbd na power mode 8 peripheral currents uart0 i uart0 v bat = 2.4 v, t a = 25 c ? 120 tbd na v bat = 3.8 v, t a = 25 c ? 195 tbd na lcd0 6 , no segments active i lcd0 v bat = 2.4 v, t a = 25 c ? 395 tbd na v bat = 3.8 v, t a = 25 c ? 495 tbd na table 3.2. power consumption (continued) parameter symbol condition min typ max unit notes: 1. currents are additive. for example, where i bat is specified and the mode is not mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 2. i ncludes all peripherals that cannot have clocks gated in the clock control module. 3. includes ldo and pll0osc (>20 mhz) or lposc0 (< 20 mhz) supply current 4. internal digital and memory ldos scaled to optimal output voltage. 5. includes lfo supply current. 6. lcd0 current does not include switching currents for external load. 7. idac output current not included. 8. does not include lc tank circuit. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 12 rev 0.4 lcd0 6 , all (4 x 40) segments active i lcd0 v bat = 2.4 v, t a = 25 c ? 580 tbd na v bat = 3.8 v, t a = 25 c ? 800 tbd na advanced capture counter (acctr0), lc single-ended mode, relative to sampling frequency 8 i acctr v bat = 2.4 v, t a = 25 c, cpmd = 01 ? 1.11 tbd na/hz v bat = 3.8 v, t a = 25 c, cpmd = 01 ? 1.44 tbd na/hz v bat = 2.4 v, t a = 25 c, cpmd = 10 ? 1.45 tbd na/hz v bat = 3.8 v, t a = 25 c, cpmd = 10 ? 1.82 tbd na/hz v bat = 2.4 v, t a = 25 c, cpmd = 11 ? 2.15 tbd na/hz v bat = 3.8 v, t a = 25 c, cpmd = 11 ? 2.54 tbd na/hz advanced capture counter (acctr0), lc dual or quadrature mode, relative to sampling frequency 8 i acctr v bat = 2.4 v, t a = 25 c, cpmd = 01 ? 1.39 tbd na/hz v bat = 3.8 v, t a = 25 c, cpmd = 01 ? 1.89 tbd na/hz v bat = 2.4 v, t a = 25 c, cpmd = 10 ? 2.08 tbd na/hz v bat = 3.8 v, t a = 25 c, cpmd = 10 ? 2.59 tbd na/hz v bat = 2.4 v, t a = 25 c, cpmd = 11 ? 3.47 tbd na/hz v bat = 3.8 v, t a = 25 c, cpmd = 11 ? 4.03 tbd na/hz analog peripheral supply currents pll0 oscillator (pll0osc) i pllosc operating at 49 mhz ? 1.4 1.6 ma low-power oscillator (lposc0) i lposc operating at 20 mhz ? 25 tbd a operating at 2.5 mhz ? 25 tbd a low-frequency oscillator (lfosc0) i lfosc operating at 16.4 khz ? 190 tbd na table 3.2. power consumption (continued) parameter symbol condition min typ max unit notes: 1. currents are additive. for example, where i bat is specified and the mode is not mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 2. i ncludes all peripherals that cannot have clocks gated in the clock control module. 3. includes ldo and pll0osc (>20 mhz) or lposc0 (< 20 mhz) supply current 4. internal digital and memory ldos scaled to optimal output voltage. 5. includes lfo supply current. 6. lcd0 current does not include switching currents for external load. 7. idac output current not included. 8. does not include lc tank circuit. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 13 external oscillator (extosc0) i extosc freqcn = 111 ? 3.8 tbd ma freqcn = 110 ? 840 tbd a freqcn = 101 ? 185 tbd a freqcn = 100 ? 65 tbd a freqcn = 011 ? 25 tbd a freqcn = 010 ? 10 tbd a freqcn = 001 ? 5 tbd a freqcn = 000 ? 3 tbd a saradc0 i saradc sampling at 1 msps, internal vref used ? 1.2 tbd ma sampling at 250 ksps, lowest power mode settings. ? 390 tbd a temperature sensor i tsense ? 75 tbd a internal sar reference i reffs normal power mode ? 680 ? a normal power mode ? 160 ? a vref0 i refp ? 80 ? a comparator 0 (cmp0), comparator 1 (cmp1) i cmp cmpmd = 11 ? 0.5 tbd a cmpmd = 10 ? 3 tbd a cmpmd = 01 ? 10 tbd a cmpmd = 00 ? 25 tbd a idac0 7 i idac ? 70 tbd a voltage supply monitor (vmon0) i vmon ? 10 tbd a flash current on vbat write operation i flash-w ? ? 8 ma erase operation i flash-e ? ? 15 ma table 3.2. power consumption (continued) parameter symbol condition min typ max unit notes: 1. currents are additive. for example, where i bat is specified and the mode is not mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 2. i ncludes all peripherals that cannot have clocks gated in the clock control module. 3. includes ldo and pll0osc (>20 mhz) or lposc0 (< 20 mhz) supply current 4. internal digital and memory ldos scaled to optimal output voltage. 5. includes lfo supply current. 6. lcd0 current does not include switching currents for external load. 7. idac output current not included. 8. does not include lc tank circuit. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 14 rev 0.4 table 3.3. power mode wake up times parameter symbol condition min typ max unit power mode 2 or 6 wake time t pm2 4 ? 5 clocks power mode 3 fast wake time t pm3fw ? 425 ? s power mode 8 wake time t pm8 ? 3.8 ? s notes: 1. wake times are specified as the time from the wake source to the execution phase of the first instruction following wfi. this includes latency to recognize the wake event and fetch the first instruction (assuming wait states = 0). table 3.4. reset and supply monitor parameter symbol condition min typ max unit v bat high supply monitor threshold (vbathithen = 1) v vbatmh early warning ? 2.20 ? v reset 1.95 2.05 2.1 v v bat low supply monitor threshold (vbathithen = 0) v vbatml early warning ? 1.85 ? v reset 1.70 1.74 1.77 v power-on reset (por) threshold v por rising voltage on v bat ? 1.4 ? v falling voltage on v bat tbd 1 tbd v v bat ramp time t rmp time to v bat > 1.8 v 10 ? 3000 s reset delay from por t por relative to v bat > v por 3 ? 100 ms reset delay from non-por source t rst time between release of reset source and code execution ? ? tbd s reset low time to generate reset t rstl 50 ? ? ns missing clock detector response time (final rising edge to reset) t mcd f ahb > 1 mhz ? 0.5 1.5 ms missing clock detector trigger ? frequency f mcd ? 2.5 10 khz v bat supply monitor turn-on time t mon ? 2 ? s www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 15 table 3.5. on-chip regulators parameter symbol condition min typ max unit dc-dc buck converter input voltage range v dcin 1.8 ? 3.8 v input supply to output voltage differ - ential (for regulation) v dcreg 0.45 ? ? v output voltage range v dcout 1.25 ? 3.8 v output voltage accuracy v dcacc ? 25 ? mv output current i dcout ? ? 90 ma inductor value 1 l dc 0.47 0.56 0.68 h inductor current rating i ldc i load < 50 ma 450 ? ? ma i load > 50 ma 550 ? ? ma output capacitor value c dcout 1 2.2 10 f input capacitor value 2 c dcin ? 4.7 ? f load regulation r load ? 0.03 ? mv/ma maximum dc load current during startup i dcmax ? ? 5 ma switching clock frequency f dcclk 1.9 2.9 3.8 mhz local oscilla tor frequency f dcosc 2.4 2.9 3.4 mhz ldo regulators output range 3 v ldo 0.8 ? 1.9 v output settings in pm8 (all ldos) v ldo 1.8 v < v bat < 2.9 v 1.5 v 1.95 v < v bat < 3.5 v 1.8 v 2.0 v < v bat < 3.8 v 1.9 v memory ldo output setting during flash programming v ldomem 1.8 ? 1.9 v analog ldo output setting during normal operation 4 v ldoana 1.8 v ldo output voltage accuracy v ldoacc ? 25 ? mv notes: 1. see reference manual for recommended inductors. 2. recommended: x7r or x5r ceramic capacitors with low esr . example: murata grm21br71c225k with esr < 10 m ? (@ frequency > 1 mhz). 3. output range represents the programmabl e output range, and does not refl ect the minimum voltage under all conditions. 4. analog peripheral specific ations assume a 1.8 v output on the analog ldo. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 16 rev 0.4 table 3.6. flash memory parameter symbol condition min typ max unit write time t write one 16-bit half word 20 21 22 s erase time t erase one page 20 21 22 ms t erall full device 20 21 22 ms endurance (write/erase cycles) n we 20k tbd ? cycles retention* t ret t a = 85 c, 1k cycles tbd tbd ? years *note: additional data retention information is published in the quarterly quality and reliability report. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 17 table 3.7. internal oscillators parameter symbol condition min typ max unit phase-locked loop (pll0osc) calibrated output frequency (free-running output mode, range = 2) f pll0osc full temperature and supply range 48.3 49 49.7 mhz power supply sensitivity (free-running output mode, range = 2) pss pll0osc t a = 25 c, fout = 49 mhz ? 300 ? ppm/v temperature sensitivity (free-running output mode, range = 2) ts pll0osc v bat = 3.3 v, fout = 49 mhz ? 50 ? ppm/c adjustable output frequency range f pll0osc 23 ? 50 mhz lock time t pll0lock f ref = 20 mhz, f pll0osc = 50 mhz m=39, n=99, lockth = 0 ? 2.75 ? s f ref = 2.5 mhz, f pll0osc = 50 mhz m=19, n=399, lockth = 0 ? 9.45 ? s f ref = 32.768 khz, f pll0osc = 50 mhz m=0, n=1524, lockth = 0 ? 92 ? s low power oscillator (lposc0) oscillator frequency f lposc full temperature and supply range 19 20 21 mhz divided oscillator frequency f lposcd full temperature and supply range 2.375 2.5 2.625 mhz power supply sensitivity pss lposc t a = 25 c ? 0.5 ? %/v temperature sensitivity ts lposc v bat = 3.3 v ? 55 ? ppm/c low frequency oscillator (lfosc0) oscillator frequency f lfosc full temperature and supply range 13.4 16.4 19.7 khz t a = 25 c, v bat = 3.3 v 15.8 16.4 17.3 khz power supply sensitivity pss lfosc t a = 25 c ? 2.4 ? %/v temperature sensitivity ts lfosc v bat = 3.3 v ? 0.2 ? %/c www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 18 rev 0.4 rtc0 oscillator (rtc0osc) missing clock detector trigger frequency f rtcmcd ? 8 15 khz rtc robust duty cycle range dc rtc 25 ? 55 % table 3.8. external oscillator parameter symbol condition min typ max unit external input cmos clock frequency f cmos 0* ? 50 mhz external crystal frequency f xtal 0.010 ? 25 mhz external input cmos clock high time t cmosh 9 ? ? ns external input cmos clock low time t cmosl 9 ? ? ns low power mode charge pump ? supply range(input from v bat ) v bat 2.4 ? 3.8 v *note: minimum of 10 khz when debugging. table 3.7. internal oscillators (continued) parameter symbol condition min typ max unit www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 19 table 3.9. sar adc parameter symbol condition min typ max unit resolution n bits 12 bit mode 12 bits 10 bit mode 10 bits supply voltage requirements (vbat) v adc high speed mode 2.2 ? 3.8 v low power mode 1.8 ? 3.8 v throughput rate (high speed mode) f s 12 bit mode ? ? 250 ksps 10 bit mode ? ? 1 msps throughput rate (low power mode) f s 12 bit mode ? ? 62.5 ksps 10 bit mode ? ? 250 ksps tracking time t trk high speed mode 230 ? ? ns low power mode 450 ? ? ns sar clock frequency f sar high speed mode ? ? 16.24 mhz low power mode ? ? 4 mhz conversion time t cnv 10-bit conversion, sar clock = 16 mhz, apb clock = 40 mhz. 762.5 ns sample/hold capacitor c sar gain = 1 ? 5 ? pf gain = 0.5 ? 2.5 ? pf input pin capacitance c in high quality inputs ? 18 ? pf normal inputs ? 20 ? pf input mux impedance r mux high quality inputs ? 300 ? ? normal inputs ? 550 ? ? voltage reference range v ref 1 ? v bat v input voltage range* v in gain = 1 0 ? v ref v gain = 0.5 0 ? 2xv ref v power supply rejection ratio psrr adc ? 70 ? db dc performance integral nonlinearity inl 12 bit mode ? 1 1.9 lsb 10 bit mode ? 0.2 0.5 lsb differential nonlinearity ? (guaranteed monotonic) dnl 12 bit mode ?1 0.7 1.8 lsb 10 bit mode ? 0.2 0.5 lsb offset error (using agnd) e off 12 bit mode, vref =2.4 v ?2 0 2 lsb 10 bit mode, vref =2.4 v ?1 0 1 lsb www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 20 rev 0.4 offset temperatue coefficient tc off ? 0.004 ? lsb/c slope error e m 12 bit mode ?0.07 ?0.02 0.02 % dynamic performance (10 khz sine wave input 1db below full scale, max throughput) signal-to-noise snr 12 bit mode 62 66 ? db 10 bit mode 58 60 ? db signal-to-noise plus distortion sndr 12 bit mode 62 66 ? db 10 bit mode 58 60 ? db total harmonic distortion (up to 5th harmonic) thd 12 bit mode ? 78 ? db 10 bit mode ? 77 ? db spurious-free dynamic range sfdr 12 bit mode ? ?79 ? db 10 bit mode ? ?74 ? db *note: absolute input pin voltage is limited by the lower of the supply at vbat and vio. table 3.9. sar adc (continued) parameter symbol condition min typ max unit www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 21 table 3.10. idac parameter symbol condition min typ max unit static performance resolution n bits 10 bits integral nonlinearity inl ? 0.5 2 lsb differential nonlinearity (guaranteed monotonic) dnl ? 0.5 1 lsb output compliance range v ocr ? ? v bat ? 1.0 v full scale output current i out 2 ma range, t a = 25 c tbd 2.046 tbd ma 1 ma range, t a = 25 c tbd 1.023 tbd ma 0.5 ma range, t a = 25 c tbd 511.5 tbd a offset error e off ? 250 ? na full scale error tempco tc fs 2 ma range ? 100 ? ppm/c vbat power supply rejection ratio 2 ma range ? -220 ? ppm/v test load impedance (to v ss ) r test ? 1 ? k ? dynamic performance output settling time to 1/2 lsb min output to max out - put ? 1.2 ? s startup time ? 3 ? s www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 22 rev 0.4 table 3.11. acctr (advanced capture counter) parameter symbol condition min typ max unit lc comparator response time, cmpmd = 11 ? (highest speed) t resp0 +100 mv differential ? 100 ? ns ?100 mv differential ? 150 ? ns lc comparator response time, cmpmd = 00 ? (lowest power) t resp3 +100 mv differential ? 1.4 ? s ?100 mv differential ? 3.5 ? s lc comparator positive hysteresis mode 0 (cpmd = 11) hys cp+ cmphyp = 00 ? 0.37 ? mv cmphyp = 01 ? 7.9 ? mv cmphyp = 10 ? 16.7 ? mv cmphyp = 11 ? 32.8 ? mv lc comparator negative hysteresis mode 0 (cpmd = 11) hys cp- cmphyn = 00 ? 0.37 ? mv cmphyn = 01 ? ?7.9 ? mv cmphyn = 10 ? ?16.1 ? mv cmphyn = 11 ? ?32.7 ? mv lc comparator positive hysteresis mode 1 (cpmd = 10) hys cp+ cmphyp = 00 ? 0.47 ? mv cmphyp = 01 ? 5.85 ? mv cmphyp = 10 ? 12 ? mv cmphyp = 11 ? 24.4 ? mv lc comparator negative hysteresis mode 1 (cpmd = 10) hys cp- cmphyn = 00 ? 0.47 ? mv cmphyn = 01 ? ?6.0 ? mv cmphyn = 10 ? ?12.1 ? mv cmphyn = 11 ? ?24.6 ? mv lc comparator positive hysteresis mode 2 (cpmd = 01) hys cp+ cmphyp = 00 ? 0.66 ? mv cmphyp = 01 ? 4.55 ? mv cmphyp = 10 ? 9.3 ? mv cmphyp = 11 ? 19 ? mv lc comparator negative hysteresis mode 2 (cpmd = 01) hys cp- cmphyn = 00 ? 0.6 ? mv cmphyn = 01 ? ?4.5 ? mv cmphyn = 10 ? ?9.5 ? mv cmphyn = 11 ? ?19 ? mv www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 23 lc comparator positive hysteresis mode 3 (cpmd = 00) hys cp+ cmphyp = 00 ? 1.37 ? mv cmphyp = 01 ? 3.8 ? mv cmphyp = 10 ? 7.8 ? mv cmphyp = 11 ? 15.6 ? mv lc comparator negative hysteresis mode 3 (cpmd = 00) hys cp- cmphyn = 00 ? 1.37 ? mv cmphyn = 01 ? ?3.9 ? mv cmphyn = 10 ? ?7.9 ? mv cmphyn = 11 ? ?16 ? mv lc comparator input range (acctr0_lcin pin) v in ?0.25 ? v bat +0. 25 v lc comparator common-mode rejection ratio cmrr cp ? 75 ? db lc comparator po wer supply rejec - tion ratio psrr cp ? 72 ? db lc comparator input offset voltage v off t a = 25 c ?10 0 10 mv lc comparator input offset tempco tc off ? 3.5 ? v/c reference dac offset error dac eoff ?1 ? 1 lsb reference dac full scale output dac fs low range ? v io /8 ? v high range ? v io ? v reference dac step size dac lsb low range (48 steps) ? v io /384 ? v high range (64 steps) ? v io /64 ? v lc oscillator period t lcosc ? 25 ? ns lc bias output impedance r lcbias 10 a load ? 1 ? k ? lc bias drive strength i lcbias ? ? 2 ma pull-up resist or tolerance r tol puval[4:2] = 0 to 6 -15 ? 15 % puval[4:2] = 7 -10 ? 10 % table 3.11. acctr (advanced capture counter) (continued) parameter symbol condition min typ max unit www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 24 rev 0.4 table 3.12. voltage reference electrical characteristics parameter symbol condition min typ max unit internal fast settling reference output voltage v reffs ?40 to +85 c, v bat = 1.8?3.8 v 1.6 1.65 1.7 v temperature coefficient tc reffs ? 50 ? ppm/c turn-on time t reffs ? ? 1.5 s power supply rejection psrr reffs ? 400 ? ppm/v internal precision reference valid supply range v bat vref2x = 0 1.8 ? 3.8 v vref2x = 1 2.7 ? 3.8 v output voltage v refp 25 c ambient, vref2x = 0 1.17 1.2 1.23 v 25 c ambient, vref2x = 1 2.35 2.4 2.45 v short-circuit current i sc ? ? 10 ma temperature coefficient tc vrefp ? 35 ? ppm/c load regulation lr vrefp load = 0 to 200 a to vrefgnd ? 4.5 ? ppm/a load capacitor c vrefp load = 0 to 200 a to vrefgnd 0.1 ? ? f turn-on time t vrefpon 4.7 f tantalum, 0.1 f ceramic bypass ? 3.8 ? ms 0.1 f ceramic bypass ? 200 ? s power supply rejection psrr vrefp vref2x = 0 ? 320 ? ppm/v vref2x = 1 ? 560 ? ppm/v external reference input current i extref sample rate = 250 ksps; vref = 3.0 v ? 5.25 ? a table 3.13. temperature sensor parameter symbol condition min typ max unit offset v off t a = 0 c ? 760 ? mv offset error* e off t a = 0 c ? 14 ? mv slope m ? 2.77 ? mv/c slope error* e m ? 25 ? v/c linearity ? 1 ? c turn-on time ? 1.8 ? s *note: absolute input pin voltage is limited by the lower of the supply at vbat and vio. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 25 table 3.14. comparator parameter symbol condition min typ max unit response time, cmpmd = 00 ? (highest speed) t resp0 +100 mv differential ? 100 ? ns ?100 mv differential ? 150 ? ns response time, cmpmd = 11 ? (lowest power) t resp3 +100 mv differential ? 1.4 ? s ?100 mv differential ? 3.5 ? s positive hysteresis mode 0 (cpmd = 00) hys cp+ cmphyp = 00 ? 0.37 ? mv cmphyp = 01 ? 7.9 ? mv cmphyp = 10 ? 16.7 ? mv cmphyp = 11 ? 32.8 ? mv negative hysteresis mode 0 (cpmd = 00) hys cp- cmphyn = 00 ? 0.37 ? mv cmphyn = 01 ? ?7.9 ? mv cmphyn = 10 ? ?16.1 ? mv cmphyn = 11 ? ?32.7 ? mv positive hysteresis mode 1 (cpmd = 01) hys cp+ cmphyp = 00 ? 0.47 ? mv cmphyp = 01 ? 5.85 ? mv cmphyp = 10 ? 12 ? mv cmphyp = 11 ? 24.4 ? mv negative hysteresis mode 1 (cpmd = 01) hys cp- cmphyn = 00 ? 0.47 ? mv cmphyn = 01 ? ?6.0 ? mv cmphyn = 10 ? ?12.1 ? mv cmphyn = 11 ? ?24.6 ? mv positive hysteresis mode 2 (cpmd = 10) hys cp+ cmphyp = 00 ? 0.66 ? mv cmphyp = 01 ? 4.55 ? mv cmphyp = 10 ? 9.3 ? mv cmphyp = 11 ? 19 ? mv negative hysteresis mode 2 (cpmd = 10) hys cp- cmphyn = 00 ? 0.6 ? mv cmphyn = 01 ? ?4.5 ? mv cmphyn = 10 ? ?9.5 ? mv cmphyn = 11 ? ?19 ? mv www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 26 rev 0.4 positive hysteresis mode 3 (cpmd = 11) hys cp+ cmphyp = 00 ? 1.37 ? mv cmphyp = 01 ? 3.8 ? mv cmphyp = 10 ? 7.8 ? mv cmphyp = 11 ? 15.6 ? mv negative hysteresis mode 3 (cpmd = 11) hys cp- cmphyn = 00 ? 1.37 ? mv cmphyn = 01 ? ?3.9 ? mv cmphyn = 10 ? ?7.9 ? mv cmphyn = 11 ? ?16 ? mv input range (cp+ or cp?) v in ?0.25 ? v bat +0.25 v input pin capacitance c cp ? 7.5 ? pf common-mode rejection ratio cmrr cp ? 75 ? db power supply rejection ratio psrr cp ? 72 ? db input offset voltage v off t a = 25 c ?10 0 10 mv input offset tempco tc off ? 3.5 ? v/c reference dac resolution n bits 6 bits table 3.15. lcd0 parameter symbol condition min typ max unit charge pump output voltage error v cperr ? 50 ? mv lcd clock frequency f lcd 16 ? 33 khz table 3.14. comparator (continued) parameter symbol condition min typ max unit www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 27 table 3.16. port i/o parameter symbol condition min typ max unit output high voltage (pb0, pb1, pb3, or pb4) v oh low drive, i oh = ?1 ma v io ? 0.7 ? ? v low drive, i oh = ?10 a v io ? 0.1 ? ? v high drive, i oh = ?3 ma v io ? 0.7 ? ? v high drive, i oh = ?10 a v io ? 0.1 ? ? v output high voltage (pb2) v oh low drive, i oh = ?1 ma v iorf ? 0.7 ? ? v low drive, i oh = ?10 a v iorf ? 0.1 ? ? v high drive, i oh = ?3 ma v iorf ? 0.7 ? ? v high drive, i oh = ?10 a v iorf ? 0.1 ? ? v output low voltage (any port i/o pin or reset 1 ) v ol low drive, i ol = 1.4 ma ? ? 0.6 v low drive, i ol = 10 a ? ? 0.1 v high drive, i ol = 8.5 ma ? ? 0.6 v high drive, i ol = 10 a ? ? 0.1 v input high voltage (pb0, pb1, pb3, pb4 or reset ) v ih v io ? 0.6 ? ? v input high voltage (pb2) v ih v iorf ? 0.6 ? ? v input low voltage any port i/o pin or reset ) v il ? ? 0.6 v pin capacitance c io ? tbd ? pf weak pull-up current 2 (per pin) i pu v io or v iorf = 1.8 -6 -3.5 -2 a v io or v iorf = 3.6 -30 -20 -10 a input leakage ? (pullups off or analog) i lk 0 < v in < v io or v iorf -1 ? 1 a notes: 1. specifications for reset v ol adhere to the low drive setting. 2. on the sim3l1x6 and sim3l1x4 devices, the swv pin will ha ve double the weak pull-up current specified whenever the device is held in reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 28 rev 0.4 3.2. thermal conditions table 3.17. thermal conditions parameter symbol condition min typ max unit thermal resistance* ? ja tqfp-80 packages ? 40 ? c/w tfbga-80 packages ? tbd ? c/w qfn-64 packages ? 25 ? c/w tqfp-64 packages ? 30 ? c/w qfn-40 packages ? 30 ? c/w *note: thermal resistance assumes a multi-layer pcb with the exposed pad soldered to a topside pcb pad. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 29 3.3. absolute maximum ratings stresses above those lis ted under table 3.18 may cause permanent damage to the device. this is a stress rating only and functional operation of the de vices at those or any other conditions above those indicated in the operation listings of this specification is not im plied. exposure to maximum rating condit ions for extended periods may affect device reliability. table 3.18. absolute maximum ratings parameter symbol condition min max unit ambient temperature under bias t bias ?55 125 c storage temperature t stg ?65 150 c voltage on vbat/vbatdc v bat v ss ?0.3 4.2 v voltage on vdc v dc v ssdc ?0.3 4.2 v voltage on vdrv v drv v ss ?0.3 4.2 v voltage on vio v io v ss ?0.3 4.2 v voltage on viorf v iorf v ss ?0.3 4.2 v voltage on vlcd v lcd v ss ?0.3 4.2 v voltage on i/o (pb0, pb1, pb3, pb4) or reset 2 v in v io > 3.3 v v ss ?0.3 5.8 v v io < 3.3 v v ss ?0.3 v io +2.5 v voltage on pb2 i/o pins 2 v in v iorf > 3.3 v v ss ?0.3 5.8 v v iorf < 3.3 v v ss ?0.3 v iorf +2.5 v total current sunk into supply pins i supp vbat/vbatdc, vio, viorf, vdrv, vdc, vlcd ? 400 ma total current sourced out of ground pins i vss v ss, v ssdc 400 ? ma current sourced or sunk by any i/o pin i pio all i/o and reset ?100 100 ma power dissipation at t a = 85 c p d tqfp-80 packages ? tbd mw tfbga-80 packages ? tbd mw qfn-64 packages ? 800 mw tqfp-64 packages ? 650 mw qfn-40 packages ? 650 mw notes: 1. vss and vssdc provide separate return cu rrent paths for device su pplies, but are not isolat ed. they must always be connected to the same potential on board. 2. exceeding the minimum v io voltage may cause current to flow through adjacent device pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 30 rev 0.4 4. precision32? sim3l1xx system overview the sim3l1xx precision32? devices are fully integrated, mixed-signal system-on-a-chip mcus. highlighted features are listed below. refer to table 5.1 for specif ic product feature selection and part ordering numbers. ?? core: ?? 32-bit arm cortex-m3 cpu. ?? 50 mhz maximum operating frequency. ?? branch target cache and prefetch buf fers to minimize wait states. ?? memory: 32?256 kb flash; in-system programmable, 8?32 kb sram configurable to retention mode in 4 kb blocks. blocks configured to retention mo de preserve state in the low power pm8 mode. ?? power: ?? three adjustable low drop-out (ldo) regulators. ?? dc-dc buck converter allows dynamic voltage scaling for maximum efficiency (250 mw output). ?? power-on reset circuit and brownout detectors. ?? power management unit (pmu). ?? specialized charge pump reduces po wer consumption in low power modes. ?? process/voltage/temperature (pvt) monitor. ?? register state retention in lowest power mode. ?? i/o: up to 62 contiguous 5 v tolerant i/o pins and one flexible peripheral crossbar. ?? clock sources: ?? internal oscillator with pll: 23 ? 50 mhz with 1.5% accuracy in free-running mode. ?? low-power internal oscillator: 20 mhz. ?? low-frequency internal oscillator: 16.4 khz. ?? external rtc crystal oscillator: 32.768 khz. ?? external oscillator: crystal, rc, c, cmos clock. ?? integrated lcd controller (4x40). ?? data peripherals: ?? 10-channel dma controller. ?? 3 x data transfer managers. ?? 128/192/256-bi t hardware aes encryption. ?? crc with programmable 16-bit poly nomial, one 32-bit polynomial, and bus snooping capability. ?? encoder / decoder. ?? timers/counters: ?? 3 x 32-bit timers. ?? 1 x enhanced programmable counter array (epca). ?? real time clock (rtc0). ?? low power timer. ?? watchdog timer. ?? low power mode advanced capture counter (acctr). ?? communications peripherals: ?? 1 x usart with irda and iso7816 smartcard support. ?? 1 x uart that operates in low power mode (pm8). ?? 2 x spis. ?? 1 x i2c. ?? analog: ?? 1 x 12-bit analog-to-digital converter (saradc). ?? 1 x 10-bit digital-to-analog converter (idac). ?? 2 x low-current comparators (cmp). ?? on-chip debugging with on-chip power-on reset, voltage supply monitor, watchdog timer, and clock osc illators, the sim 3l1xx devices are truly stand-alone system-on-a-chip solutions. the flas h memory is reprogrammable in-circuit, providing non- volatile data storage and allowing field upgrades of the firmware. user firmware ha s complete control of all www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 31 peripherals and may individually shut down and gate th e clocks of any or all peripherals for power savings. the on-chip debugging interface (swj-dp) allows non-intrusive (uses no on-chi p resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. all analog and digital peripherals are fully functional while debugging. each device is specified for 1.8 to 3. 8 v operation over the industrial temperature range (?40 to +85 c). the sim3l1xx devices are available in 40-pin or 64-pin qf n, 64-pin or 80-pin tqfp, and 80-pin tfbga packages. all package options are lead-free and rohs compliant. see t able 5.1 for ordering information. a block diagram is included in figure 4.1. figure 4.1. precision32? sim3l1xx family block diagram voltage supply monitor (vmon0) watchdog timer (wdtimer0) arm cortex m3 core debug / programming hardware dma 10-channel controller peripheral crossbar power on reset / pmu ahb apb power memory dma support available for these peripherals clock control clocking low frequency osc illator (lfosc0) low power oscillator (lposc0) real-time clock oscillator (rtc0osc) external oscillator control (extosc0) phase-locked loop (pll0osc) peripheral clock control (clkctrl) dc-dc buck converter (dcdc0) data transfer manager dtm0 dtm1 dtm2 ldo0 low power mode charge pump power management unit (pmu) 32/64/128/256 kb flash 8/16/32 kb configurable retention ram digital ldo memory ldo analog ldo i/o standard 5 v tolerant i/o pins crossbar analog comparator 0 comparator 1 idac0 saradc0 digital usart0 uart0 i2c0 spi1 spi0 epca0 timer 0 low power timer (lptimer0) aes0 crc0 encdec0 advanced capture counter (acctr0) timer 2 timer 1 4x40 segment lcd controller www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 32 rev 0.4 4.1. power the sim3l1xx devices include a dc-dc buck converter that ca n take an input from 1.8?3.8 v and create an output from 1.25?3.8 v. in addition, sim3l1xx devices include th ree low dropout regulators as part of the ldo0 module: one ldo powers the analog subsystems, one ldo powers the flash and sram memory at 1.8 v, and one ldo powers the digital and core circuitry. each of thes e regulators can be independently powered from the dc-dc converter or directly from the battery voltage, and thei r outputs are adjustable to conserve system power. sim3l1xx devices also include a low power charge pump in the pmu module for use in low power modes (pm8) to further reduce the power consumption of the device. figure 4.2 shows the power system configuration of these devices. figure 4.2. sim3l1xx power 4.1.1. dc-dc buck converter (dcdc0) sim3l1xx devices include an on-chip st ep-down dc-dc converter to efficiently utilize the energy stored in the battery, thus extending the operational life time. the dc-dc converter is a switching buck converter with a programmable output voltage that should be at least 0.45 v lower than the input battery voltage; if this criteria is not met and the converter can no longer operate, the output of the dc-dc converter autom atically connects to the battery. the dc-dc converter can supply up to 100 ma and can be used to power the mcu and/or external devices in the system. the dc-dc conver ter has a built in voltage reference and oscilla tor and will automatically limit or turn off the switching activity in case the peak indu ctor current rises beyond a safe limit or the output voltage rises above the programmed target value. this allows the dc-dc converte r output to be safely overdriven by a secondary power source (when available) in order to preserve battery lif e. when enabled, the dc-dc converter can source current into the output capacitor, but cannot sink current. the dc-dc converter includes the following features: ?? efficiently utilizes the energy stored in a battery, extend ing its operational lifetime. ?? input range: 1.8 to 3.8 v. ?? output range: 1.25 to 3.8 v in 50 mv (1.25?1.8 v) or 100 mv (1.8?3.8 v) steps. ?? supplies up to 100 ma. ?? includes a voltage refe rence and an oscillator. sim3l1xx device vdc ind vbat/vbatdc vssdc vss dc-dc converter vdrv low power mode charge pump to pm8 peripherals ldo0 digital ldo memory ldo analog ldo to digital and core to memory to analog www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 33 ?? supports synchronizing the regulator switching with the system clock. ?? automatically limits the pe ak inductor current if the load current rises beyond a safe limit. ?? automatically goes into bypass mode if the battery voltage cannot provide sufficient headroom. ?? sources current, but cannot sink current. 4.1.2. three low dropout ldo regulators (ldo0) the sim3l1xx devices include one ldo0 module with three low dropout regulators. each of these regulators have independent switches to select the battery voltage or the output of the dc-dc converte r as the input to each ldo, and an adjustable output voltage. the ldos consume little power and prov ide flexibility in choosing a power supp ly for the system. each regulator can be independently adjusted between 0.8 and 1.9 v output. 4.1.3. voltage supply monitor (vmon0) the sim3l1xx devices include a voltage supply monitor th at can monitor the main supply voltage. this module includes the following features: ?? main supply ?vbat low? (vbat below the early warning threshold) notification. ?? holds the device in reset if the main vbat supply drops below the vbat reset threshold. the voltage supply monitor allows devi ces to function in known, safe operating conditions without the need for external hardware. 4.1.4. power management unit (pmu) the power management unit on the sim3l1xx manages th e power systems of the device. it manages the power- up sequence during power on and the wake up sources for pm8. on power-up, the pmu ensures the core voltages are a proper value before core instruction execution begins. the vdrv pin powers external circuitry from either the vbat battery input voltage or the output of the dc-dc converter on vdc. the pmu includes an internal switch to select one of these sources for the vdrv pin. the pmu has a specialized vbat-divided-by-2 charge pump that can power some internal modules while in pm8 to save power. the pmu module includes the following features: ?? provides the enable or disable for the analog power system, including the three ldo regulators. ?? up to 14 pin wake inputs can wake the device from power mode 8. ?? the low power timer, rtc0 (alarm s and oscillator failure), comparat or 0, advanced capture counter, lcd0 vbat monitor, uart0, low power mode charge pump failure, and the reset pin can also serve as wake sources for power mode 8. ?? controls which 4 kb ram blocks are retained while in power mode 8. ?? provides a pmu_asleep signal to a pin as an indicator that the device is in pm8. ?? specialized charge pump to reduce power consumption in pm8. ?? provides control for the internal switch between vbat and vdc to power the vdrv pin for external circuitry. 4.1.5. device power modes the sim3l1xx devices feature seven low power modes in addition to normal operating mode. several peripherals provide wake up sources for these low power modes, in cluding the low power timer (lptimer0), rt c0 (alarms and oscillator failure notifi cation), comparator 0 (c mp0), advanced capture counter (acctr0), lcd vbat monitor (lcd0), uart0, low power mode charge pump failure, and pmu pin wake. in addition, all peripherals can have their clocks disabl ed to reduce power consumption whenever a peripheral is not being used using the clock control (clkctrl) registers. 4.1.5.1. normal mode (power mode 0) and power mode 4 normal mode and power mode 4 are fully operational mode s with code executing from flash memory. pm4 is the same as normal mode, but with the clocks operating at a lower speed. this enables power to be conserved by reducing the ldo regulator outputs. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 34 rev 0.4 4.1.5.2. power mode 1 and power mode 5 power mode 1 and power mode 5 are fully operational modes with code executing from ram. pm5 is the same as pm1, but with the clocks operating at a lower speed. this enables power to be conserved by reducing the ldo regulator outputs. compared with the corresponding flash operational mode (normal or pm4), the active power consumption of the device in these modes is reduced. ad ditionally, at higher speeds in pm1, the core throughput can also be increased because ramdoesnot require additiona l wait states that reduce the instruction fetch speed. 4.1.5.3. power mode 2 and power mode 6 in power mode 2 and power mode 6, the core halts and th e peripherals continue to run at the selected clock speed. pm6 is the same as pm2, but with the clocks o perating at a lower speed. this enables power to be conserved by reducing the ldo regulator outputs. to place the device in pm2 or pm6, the core should execute a wait-for-interrupt (wfi) or wait-for-eve nt (wfe) instruction. if the wfi instru ction is called from an interrupt service routine, the interrupt that wakes the device from pm2 or pm6 must be of a sufficient priority to be recognized by the core. it is recommended to perform both a dsb (data synchronization barrier) and an isb (instruction syncronization barrier) operation prior to the wfi to ens ure all bus accesses complete. when operating from the lfosc0, pm6 can achieve similar power consumption to pm3, but with faster wake times and the ability to wake on any interrupt. 4.1.5.4. power mode 3 in power mode 3 the core and peripheral clocks are halted. the available sources to wake from pm3 are controlled by the power management unit (pmu). a special fast wake option allows the core to wake faster by keeping the lfosc0 or rtc0 clock active. because the current consum ption of these blocks is mini mal, it is recommended to use the fast wake option. before entering pm3, the dma controller should be disabl ed, and the desired wake source(s) should be configured in the pmu. the sleepdeep bit in the arm system control register should be set, and the pmsel bit in the clkctrl0_config register should be cl eared to indicate that pm3 is the desired power mode. for fast wake, the core clocks (ahb and apb) should be configured to run fr om the lposc, and the pm 3 fast wake option and clock source should be sele cted in the pm3cn register. the device will enter pm3 on a wfi or wfe instruction. if the wfi inst ruction is called from an interrupt service routine, the interrupt that wakes the device from pm3 must be of a sufficient priority to be recognized by the core. it is recommended to perform both a dsb (data synchronizatio n barrier) and an isb (instruction synchronization barrier) operation prior to the wfi to ensure all bus access is complete. 4.1.5.5. power mode 8 in power mode 8, the core and most peripherals are comp letely powered down, but all registers and selected ram blocks retain their state. the ldo regulators are disabl ed, so all active circuitry operates directly from vbat. alternatively, the pmu has a specialized vbat-divided-by-2 charge pump that can power some internal modules while in pm8 to save power. the fully operational functions in this mode are: lptimer0 , rtc0, uart0 running from rtc0tclk, pmu pin wake, the advanced capture counter, and the lcd controller. this mode provides the lowest power consumption for the device, but requires an appropriate wake up source or reset to exit. the available wake up or reset sources to wake from pm8 are controlled by the power management unit (pmu). the available wake up sources are: low power timer (lpt imer0), rtc0 (alarms and oscillator failure notification), comparator 0 (cmp0), advanc ed capture counter (acctr0), lcd vbat monitor (lcd0), uart0, low power mode charge pump failure, and pmu pin wake. the available reset sources are: reset pin, vbat supply monitor, comparator 0, comparator 1, low power mode charge pump failure, rtc0 oscillator failure, or a pmu wake event. before entering pm8, the desired wa ke source(s) should be configured in the pmu. the sleepdeep bit in the arm system control register should be set, and the pm sel bit in the clkctrl0_config register should be set to indicate that pm9 is the desired power mode. the device will enter pm8 on a wfi or wfe instruction, and remain in pm9 until a reset configured by the pmu occurs. it is recommended to perform both a dsb (dat a synchronization barrier) and an isb (instruction synchronization barrier) operation prior to t he wfi to ensure all bus access is complete. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 35 4.1.5.6. power mode summary the power modes described above are summarized in table 4.1. table 3.2 and table 3.3 provide more information on the power consumption and wake up times for each mode. table 4.1. sim3l1xx power modes mode description notes normal ? core operating at full speed ? code executing from flash ? full device operation power mode 1 (pm1) ? core operating at full speed ? code executing from ram ? full device operation ? higher cpu bandwidth than pm0 (ram can operate with zero wait states at any frequency) power mode 2 (pm2) ? core halted ? ahb, apb and all peripherals operational at full speed ? fast wakeup from any interrupt source power mode 3 (pm3) ? all clocks to core and peripherals stopped ? faster wake enabled by keeping lfosc0 or rtc0tclk active ? wake on any wake source or reset source defined in the pmu power mode 4 (pm4) ? core operating at low speed ? code executing from flash ? same capabilities as pm0, operating at lower speed ? lower clock speed enables lower ldo output settings to save power power mode 5 (pm5) ? core operating at low speed ? code executing from ram ? same capabilities as pm1, operating at lower speed ? lower clock speed enables lower ldo output settings to save power power mode 6 (pm6) ? core halted ? ahb, apb and all peripherals operational at low speed ? same capabilities as pm2, operating at lower speed ? lower clock speed enables lower ldo output settings to save power ? when running from lfosc0, power is similar to pm3, but the device wakes much faster power mode 8 (pm8) ? low power sleep ? ldo regulators are disabled and all active circuitry operates directly from vbat ? the following functions are available: acctr0, rtc0, uart0 running from rtc0tclk, lptimer0, port match, and the lcd controller ? register and ram state retention ? lowest power consumption ? wake on any wake source or reset source defined in the pmu www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 36 rev 0.4 4.1.6. process/voltage/temperature monitor (timer2 and pvtosc0) the process/voltage/temperature monitor consists of two modules (timer2 and pvtosc0) designed to monitor the digital circuit performance of the sim3l1xx device. the pvt oscillator (pvtosc0) consists of two oscillators , one operating from the me mory ldo and one operating from the digital ldo. these oscillators have two indepen dent speed options and provide the clocks for two 16-bit timers in the timer2 module using the ex input. by mo nitoring the resulting coun ts of the timer2 timers, firmware can monitor the current device performance and increase the scalable ldo regulator (ldo0) output voltages as needed or decrease the output voltages to save power. the pvt monitor has the following features: ?? two separate oscillators and timers for the memo ry and digital logic voltage domains. ?? two oscillator output divider settings. ?? provides a method for monitoring digital performanc e to allow firmware to adjust the scalable ldo regulator output voltages to the lowest level possible, saving power. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 37 4.2. i/o 4.2.1. general features the sim3l1xx ports have the following features: ?? 5 v tolerant. ?? push-pull or open-drain output modes to the vio or viorf voltage level. ?? analog or digital modes. ?? option for high or low output drive strength. ?? port match allows the device to recognize a change on a port pin value. ?? internal pull-up resistors are enabled or disabled on a port-by-port basis. ?? two external interrupts with up to 16 inputs each provide monitoring capability for external signals. ?? internal pulse generator timer (pb0 only) to generate simple square waves and pulses. 4.2.2. crossbar the sim3l1xx devices have one crossbar with the following features: ?? flexible peripheral assignment to port pins. ?? pins can be individually skipped to move peripherals as needed for design or layout considerations. the crossbar has a fixed priority for each i/o function and assigns these functions to the port pins. when a digital resource is selected, the least-significant unassigned port pi n is assigned to that resource. if a port pin is assigned, the crossbar skips that pin wh en assigning the next select ed resource. additionally, th e crossbar will skip port pins whose associated bits in the pbskipen registers are set. this provides flexibility when designing a system: pins involved with sensitive analog measurements can be moved away from digital i/o, and peripherals can be moved around the chip as needed to ease layout constraints. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 38 rev 0.4 4.3. clocking the sim3l1xx devices have two system clocks: ahb and apb. the ahb clock se rvices memory pe ripherals and is derived from one of seven sources: the rtc timer clock (rtc0tclk), th e low frequency oscillator, the low power oscillator, the divided low power oscillator, the external oscillator, the pll0 osc illator, and the viorfclk pin input. in addition, a divider for the ahb clock provid es flexible clock options for the device. the apb clock services data peripherals and is sync hronized with the ahb clock. the apb cloc k can be equal to the ahb clock or set to the ahb clock divided by two. the clock control module on sim3l1xx devices allows the ahb and apb clocks to be turned off to unused peripherals to save system power. any registers in a peripheral with disabled clocks will be unable to be accessed until the clocks are enabled. most peripherals have clocks off by default after a power-on reset. figure 4.3. sim3l1xx clocking clock control apb clock ahb clock divider apb clock divider flash controller registers pbcfg and pb0/1/2/3/4 usart0 uart0 spi0 ahb clock ram dma flash dtm0 lfosc0 lposc0 rtc0tclk external oscillator viorfclk pll0 oscillator www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 39 4.3.1. pll (pll0) the pll module consists of a dedicate d digitally-controlled oscillator (dco) that can be used in free-running mode without a reference frequency, frequency-locked to a reference frequency, or phase-locked to a reference frequency. the reference frequency for frequency-lock and phase-lock modes can use one of multiple sources (including the external oscilla tor) to provide maximum fl exibility for different applic ation needs. because the pll module generates its own clock, the dco can be locked to a particular reference frequency and then moved to free-running mode to reduce system power and noise. the pll module includes the following features: ?? three output ranges with output frequencies ranging from 23 to 50 mhz. ?? multiple reference frequen cy inputs, including the rtc0 oscillator, low power oscillator, and external oscillator. ?? three output modes: free -running digitally-c ontrolled oscillator, frequency-locked, and phase-locked. ?? able to sense the rising edge or falling edge of the reference source. ?? dco frequency lsb dithering to provide finer average output frequencies. ?? spectrum spreading to reduce generated system noise. ?? low jitter and fast lock times. ?? all output frequency updates (including dithering and spectrum spreading) can be temporarily suspended using the stall bit during noise-sensitive measurements. 4.3.2. low power oscillator (lposc0) the low power oscillator is the default ahb oscillator on sim3l1xx device s and enables or dis ables automatically, as needed. the default output frequency of this o scillator is factory calibrated to 20 mhz, and a divided 2.5 mhz version of this clock is also available as an ahb clock source. the low power oscillator has the following features: ?? 20 mhz and divided 2.5 mhz frequencies available for the ahb clock. ?? automatically starts and stops as needed. 4.3.3. low frequency oscillator (lfosc0) the low frequency oscillator (l fosc0) provides a low power internal cl ock source for the rtc0 timer and other peripherals on the device. no external components are required to use the lo w frequency oscillator, and the rtc1 and rtc2 pins do not need to be shorted together. the low frequency oscillator has the following features: ?? 16.4 khz output frequency. 4.3.4. external oscillators (extosc0) the extosc0 external oscillator circuit may drive an ex ternal crystal, ceramic re sonator, capacitor, or rc network. a cmos clock may also provid e a clock input. the external oscillato r output may be selected as the ahb clock or used to clock other modules independent of the ahb clock selection. the external oscillator contro l has the following features: ?? support for external cr ystal, resonator, rc, c, or cmos oscillators. ?? support for external cmos frequencies from 10 khz to 50 mhz. ?? support for external crystal frequencies from 10 khz to 25 mhz. ?? various drive strengths for flex ible crystal oscillator support. ?? internal frequency divide-by-two option available. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 40 rev 0.4 4.4. integrated lc d controller (lcd0) sim3l1xx devices contain an lcd segment driver and on-c hip bias generation that supports static, 2-mux, 3-mux and 4-mux lcds with 1/2 or 1/3 bias. the on-chip charge pump with programmable output voltage allows software contrast control which is independent of the supply vo ltage. lcd timing is derived from the rtc timer clock (rtc0tclk) to allow precise control over the refresh rate. the sim3l1xx devices use registers to store the enabled/disabled state of individual lcd segments. all lcd waveforms are generated on-chip based on the contents of these registers with flexible waveform control to reduce power consumption wherever possible. an lcd blinking func tion is also supported on a subset of lcd segments. the lcd0 module has the following features: ?? up to 40 segment pins and 4 common pins. ?? supports lcds with 1/2 or 1/3 bias. ?? includes an on-chip charge pump with programmable outpu t that allows firmware to control the contrast independent of the supply voltage. ?? the rtc timer clock (rtc0tclk) determines the lcd timing and refresh rate. ?? all lcd waveforms are generated on-chip based on th e contents of the lcd0 registers with flexible waveform control. ?? lcd segments can be placed in a discharge state for a configurable number of rtc clock cycles before switching to the next state to reduce power consumption due to display loading. ?? includes a vbat monitor that can serve as a wakeup source for power mode 8. ?? supports four hardware auto-contrast modes: bypass, constant, minimum, and auto-bypass. ?? supports hardware blinking for up to 8 segments. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 41 4.5. data peripherals 4.5.1. 10-channel dma controller the dma facilitates autonomous periphe ral operation, allowing th e core to finish tasks more quickly without spending time polling or waiting for peripherals to interrup t. this helps reduce the overall power consumption of the system, as the device can spend more time in low-power modes. the dma controller has the following features: ?? utilizes arm primecell udma architecture. ?? implements 10 channels. ?? dma crossbar supports dtm0, dtm1, dtm2, saradc0, idac0, i2 c0, spi0, spi1, usart0, aes0, encdec0, epca0, external pin triggers, and timers. ?? supports primary, alternate, and scatter-gather data structures to implement va rious types of transfers. ?? access allowed to all ahb and apb memory space. 4.5.2. data transfer managers (dtm0, dtm1, dtm2) the data transfer manager is a module that collects dm a request signals from various peripherals and generates a series of master dma requests based on a state-driven configuration. this master request drives a set of dma channels to perform functions such as assembling and tr ansferring communication packets to external devices. this capability saves power by allowi ng the core to remain in a low power mode during complex transfer operations. a combination of simple and peripheral scatte r-gather dma configurations can be used to perform complex operations while reducing memory requirements. the dtm acts as a side channel for the peripheral?s dm a control signals. when active, it manages the dma control signals for the peripherals. when the dtmn module is inactive, the peripherals communicate directly to the dma module. the dtmn module has the following features: ?? state descriptions stored in ram with up to 15 states supported per module. ?? supports up to 15 source peripherals and up to 15 destination peripherals per module, in addition to memory or peripherals that do not require a data request. ?? includes error detection and an optional transfer timeout. ?? includes notifications for state transitions. 4.5.3. 128/192/256-bit hardware aes encryption (aes0) the basic aes block cipher is implemented in hardware. the integrated hardware support for cipher block chaining (cbc) and counter (ctr) algorithms results in identical performance, memory bandwidth, and memory footprint between the most basic electronic codebook (e cb) algorithm and these more complex algorithms. this hardware accelerator translates to more core bandwidth available for other functions or a power savings for low- power applications. the aes module includes the following features: ?? operates on 4-word (16-byte) blocks. ?? supports key sizes of 128, 192, and 256 bits for both encryption and decryption. ?? generates the round key for decryption operations. ?? all cipher operations can be performed without any firm ware intervention for multip le 4-word blocks (up to 32 kb). ?? support for various chained and stream-ciphering configurations with xor paths on both the input and output. ?? internal 4-word fifos to facilitate dma operations. ?? integrated key storage. ?? hardware acceleration for electron ic codebook (ecb), cipher-block ch aining (cbc), and counter (ctr) algorithms utilizing integrated counterblock g eneration and previous-block caching. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 42 rev 0.4 4.5.4. 16/32-bit enhanced crc (ecrc0) the ecrc0 module is designed to provide hardware calculations for flash memory verification and communications protocols. in addition to calculating a result from direct writes from firmware, the ecrc module can automatically snoop the apb bus and calculate a result from data writte n to or read from a particular peripheral. this allows for an autom atic crc result without directly fe eding data through the ecrc module. the supported 32 -bit polynomial is 0x04c11d b7 (ieee 802.3). the 16-bit polynomial is fully programmable. the crc module includes the following features: ?? support for a programmable 16-bit polynomial and one fixed 32-bit polynomial. ?? byte-level bit reversal for the crc input. ?? byte-order reorientation of words for the crc input. ?? word or half-word bit reversal of the crc result. ?? ability to configure and s eed an operation in a single register write. ?? support for single-cycle parallel (u nrolled) crc computation for 32-, 16-, or 8-bit blocks. ?? capability to crc 32 bits of da ta per peripheral bus (apb) clock. ?? automatic apb bus snooping. ?? support for dma writes using firmware request mode. 4.5.5. encoder / decoder (encdec0) the encoder / decoder module supports manchester and three-out-of-six encoding and decoding from either firmware or dma operations. this module has the following features: ?? supports manchester and three-out-of-six encoding and decoding. ?? automatic flag clearing when writing the in put or reading the output data registers. ?? writing to the input data register automatically initiates an encode or decode operation. ?? optional output in one?s complement format. ?? hardware error detection for invalid input data during decode operations, which helps reduce power consumption and packet turn-around time. ?? flexible byte swapping on the input or output data. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 43 4.6. counters/timers 4.6.1. 32-bit timer (timer0, timer1, timer2) each timer module is independent, and includes the following features: ?? operation as a single 32-bit or two independent 16-bit timers. ?? clocking options include the apb cloc k, the apb clock scaled using an 8-bit prescaler, the external oscillator, or falling edges on an external input pin (synch ronized to the apb clock). ?? auto-reload functionality in both 32-bit and 16-bit modes. timer0 and timer1 have the following features: ?? up/down count capabilit y, controlled by an external input pin. ?? rising and falling edg e capture modes. ?? low or high pulse capture modes. ?? period and duty cycle capture mode. ?? square wave output mode, which is capable of toggling an external pin at a given rate with 50% duty cycle. ?? 32- or 16-bit pulse-width modulation mode. timer2 does not support the standard input/output features of timer0 and timer1. th e timer2 ex signal is internally connected to the outputs of the pvtosc0 osc illators. timer2 can use any of the counting modes that use ex as an input, including up/down mode, edge captur e mode, and pulse capture mode. the timer2 ct signal is disconnected. 4.6.2. enhanced programmable counter array (epca0) the enhanced programmable counter array (epca0) module is a timer/counter system allowing for complex timing or waveform generation. multiple modules run from the same main counter, allowing for synchronous output waveforms. this module includes the following features: ?? three sets of channel pairs (six channels total) capable of generating complementary waveforms. ?? center- and edge-aligned waveform generation. ?? programmable dead times that ensure channel pairs are never active at the same time. ?? programmable clock divisor and multiple options for clock source selection. ?? waveform update scheduling. ?? option to function while the core is inactive. ?? multiple synchroni zation triggers. ?? pulse-width modulation (pwm) waveform generation. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 44 rev 0.4 4.6.3. real-time clock (rtc0) the rtc0 module includes a 32-bit timer that allows up to 36 hours of independent time-keeping when used with a 32.768 khz watch crystal. the rtc0 provides three alarm events in addition to a missing clock event, which can also function as interrupt, reset, or wakeup sources on sim3l1xx devices. the rtc0 module includes internal loading capacitors that are programmable to 16 discrete levels, allowing compatibility with a wid e range of crystals. the rtc0 timer clock can be buffered and routed to a port bank pin to provide an accurate, low frequency clock to other devices while the core is in its lowest power down mode. the module al so includes a low power internal low frequency oscillator that reduces low power mode current and is available for other modules to use as a clock source. the rtc0 module includes the following features: ?? 32-bit timer (supports up to 36 hours) with three separate alarms. ?? option for one alarm to auto matically reset the rtc timer. ?? missing clock detector. ?? can be used with the internal low frequency oscillator or with an external 32.768 khz crystal (no additional resistors or capacitors necessary). ?? programmable internal loading capacitors support a wide range of external 32.768 khz crystals. ?? the rtc timer clock (rtc0clk) can be buffered and routed to an i/o pin to provide an accurate, low frequency clock to other devi ces while the core is in it s lowest power down mode. ?? the rtc0 module can be powered from the low powe r mode charge pump for lowest possible power consumption while in pm8. 4.6.4. low power timer (lptimer0) the low power timer (lptimer0) module runs from the rtc timer clock (rtc0clk), allowing the lptimer0 to operate even if the ahb and apb clocks are disabled. the lptimer0 counter can increment using one of two clock sources: the clock selected by the rtc0 module, or rising or falling edges of an external signal. the low power timer includes the following features: ?? runs on low-frequency rtc timer clock (rtc0tclk). ?? the lptimer counter can increment using one of two clock sources: the rtc0tclk or rising or falling edges of an external signal. ?? overflow and threshold-match detection. ?? timer reset on threshold-match allows square-wav e generation at a variable output frequency. ?? supports pwm with configurable period and duty cycle. ?? the lptimer0 module can be powered from the low power mode charge pump for lowest possible power consumption while in pm8. 4.6.5. watchdog timer (wdtimer0) the wdtimer0 module includes a 16-bit timer, a programmable early warning interrupt, and a programmable reset period. the timer registers are protected from inadvertent access by an independent lock and key interface. the watchdog timer runs from a low frequency oscillator (lfosc0). this module includes the following features: ?? programmable timeout interval. ?? optional interrupt to warn when the watchdog timer is nearing the reset trip value. ?? lock-out feature to prevent any modification until a system reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 45 4.6.6. low power mode advanced capture counter (acctr0) the sim3l1xx devices contain a low-power advanced capt ure counter module that runs from the rtc0 clock domain and can be used with digital inputs, switch topology circuits (reed switches), or with lc resonant circuits. for switch topology circuits, the module charges one or tw o external lines by pulsing internal pull-up resistors and detecting whether the reed switch is open or closed. for lc resonant circuits, the inputs are periodically energized to produce a dampened sine wave and configurable discrimi nator circuits detect the resulting decay time-constant. the advanced capture counter has the following general features: ?? single or differential inputs supporting sing le, dual, and quadrature modes of operation. ?? variety of interrupt and pm8 wake up sources. ?? provides feedback of the direction history, cu rrent and previous states, and condition flags. the advanced capture counter has the followin g features for switch circuit topologies: ?? ultra low power input comparators. ?? supports a wide range of pull-up resistor values with a self-calibration engine. ?? asymmetrical integrators for low- pass filtering and switch debounce. ?? two 24-bit counters and two 24-bit digital threshold comparators. ?? supports switch flutter detection. for lc resonant circuit topologies, th e advanced capture counter includes: ?? separate minimum and maximum count registers and polarity, pulse, and toggle controls. ?? zone-based programmable timing. ?? two input comparators with support for a positi ve side input bias at vio divided by 2. ?? supports a configurable excitation pulse width based on a 40 mhz oscillator and timer or an external digital stop signal. ?? two 8-bit peak counters that saturate at full scal e for detecting the number of lc resonant peaks. ?? two discriminators with programmable thresholds. ?? supports a sample and hold mode for wheatstone bridges. all devices in the sim3l1xx family include the low power mode advanced capture co unter (acctr0). table 4.2 lists the supported inputs and outputs for each of the packages. table 4.2. sim3l1xx supported advanced capture counter inputs and outputs input/output sim3l1x7 sim3l1x6 sim3l1x4 acctr0_in0 ? ? ? acctr0_in1 ? ? ? acctr0_lcin0 ? ? acctr0_lcin1 ? ? ? acctr0_stop0 ? ? ? acctr0_stop1 ? ? ? acctr0_lcpul0 ? ? acctr0_lcpul1 ? ? acctr0_lcbias0 ? ? acctr0_lcbias1 ? ? acctr0_dbg0 ? ? acctr0_dbg1 ? ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 46 rev 0.4 4.7. communicat ions peripherals 4.7.1. usart (usart0) the usart uses two signals (tx and rx) to communicate se rially with an external device. in addition to these signals, the usart0 module can optionally use a cl ock (uclk) or hardware handshaking (rts and cts). the usart0 module provides the following features: ?? independent transmitter and receiver configurations with separate 16-bit baud rate generators. ?? synchronous or asynchronous tr ansmissions and receptions. ?? clock master or slave operation with programmable polarity and edge controls. ?? up to 5 mbaud (synchronous or asynchronous, tx or rx, and master or slave) or 1 mbaud smartcard (tx or rx). ?? individual enables for generated clocks during start, stop, and idle states. ?? internal transmit and receive fifo s with flush capability and support fo r byte, half-word, and word reads and writes. ?? data bit lengths from 5 to 9 bits. ?? programmable inter-packet transmit delays. ?? auto-baud detection with support for the lin sync byte. ?? automatic parity generation (with enable). ?? automatic start and stop generation (with separate enables). ?? transmit and receive hardware flow-control. ?? independent inversion correction for tx, rx, rts, and cts signals. ?? irda modulation and demodulation with programmable pulse widths. ?? smartcard ack/nack support. ?? parity error, frame error, overrun, and underrun detection. ?? multi-master and half-duplex support. ?? multiple loop-back modes supported. ?? multi-processor communications support. 4.7.2. uart (uart0) the uart uses two signals (tx and rx) to communicate serially with an external device. the uart0 module can operate in pm8 mode by taking the clock directly from the rtc0 time clock (rtc0tclk) and running from the low power mode charge pump. this will allow the system to conserve power while transmitting or receiving uart traffic. the uart0 suppor ts standard baud-rates of 9600, 4800, 2400 and 1200 in this low power mode. the uart0 module provides the following features: ?? independent transmitter and receiver configurations with separate 16-bit baud rate generators. ?? asynchronous transmissions and receptions. ?? up to 5 mbaud (tx or rx). ?? internal transmit and receive fifo s with flush capability and support fo r byte, half-word, and word reads and writes. ?? data bit lengths from 5 to 9 bits. ?? programmable inter-packet transmit delays. ?? auto-baud detection with support for the lin sync byte. ?? automatic parity generation (with enable). ?? automatic start and stop generation (with separate enables). ?? independent inversion correction for tx and rx signals. ?? parity error, frame error, overrun, and underrun detection. ?? half-duplex support. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 47 ?? multiple loop-back modes supported. ?? multi-processor communications support. ?? operates at 9600, 4800, 2400, or 1200 baud in power mode 8. 4.7.3. spi (spi0, spi1) spi is a 3- or 4-wire communication in terface that includes a clock, input da ta, output data, and an optional select signal. the spi0 and spi1 modules include the following features: ?? supports 3- or 4-wire master or slave modes. ?? supports up to 10 mhz clock in master mode and 5 mhz clock in slave mode. ?? support for all clock phase and slave select (nss) polarity modes. ?? 16-bit programmable clock rate. ?? programmable msb-first or lsb-first shifting. ?? 8-byte fifo buffers for both transmit and receive data paths to support high speed transfers. ?? support for multiple masters on the same data lines. in addition, the spi modules include several features to support autonomous dma transfers: ?? hardware nss control. ?? programmable fifo threshold levels. ?? configurable fifo data widths. ?? master or slave hardware flow control for the miso and mosi signals. spi1 is on fixed pins and supports ad ditional flow control options using a fixed input (spi1cts). neither spi1 nor the flow control input are on the crossbar. 4.7.4. i2c (i2c0) the i2c interface is a two-wire, bi-directional serial bu s. the clock and data signals operate in open-drain mode with external pull-ups to support automatic bus arbitration. reads and writes to the interface ar e byte oriented with the i2c interfac e autonomously cont rolling the serial transfer of the data. data c an be transferred at up to 1/8th of the apb cl ock as a master or slave, which can be faster than allowed by the i2c specific ation, depending on the clock source used. a method of extending the clock- low duration is available to ac commodate devices with di fferent speed capabilit ies on the same bus. the i2c interface may operate as a master and/or slave, an d may function on a bus with multiple masters. the i2c provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/ stop control and generation. the i2c0 module includes the following features: ?? standard (up to 100 kbps) and fast (400 kbps) transfer speeds. ?? can operate down to apb clock divided by 32768 or up to apb clock divided by 8. ?? support for master, slave, and multi-master modes. ?? hardware synchronization and arbitration for multi-master mode. ?? clock low extending (clock stretching) to interface with faster masters. ?? hardware support for 7-bit slave and general call address recognition. ?? firmware support for 10-bit slave address decoding. ?? ability to disable all slave states. ?? programmable clock high and low period. ?? programmable data setup/hold times. ?? spike suppression up to 2 times the apb period. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 48 rev 0.4 4.8. analog 4.8.1. 12-bit analog-to-d igital converter (saradc0) the saradc0 module on sim3l1xx devices implements the successive approximat ion register (sar) adc architecture. the key features of the module are as follows: ?? single-ended 12-bit, 10-bit, and 8-bit modes. ?? supports an output update rate of 250 k samples per second in 12-bit mode or 1 m samples per second in 10-bit mode. ?? operation in low power modes at lower conversion speeds. ?? selectable asynchronous hardware conversion trigger with hardware channel select. ?? dc offset cancellation. ?? automatic result notification with multiple programmable thresholds. ?? support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time. ?? non-burst mode operation can also automatically accu mulate multiple conversions, but a conversion start is required for each conversion. ?? conversion complete, multiple conversion complete , and fifo overflow and underflow flags and interrupts supported. ?? flexible output data formatting. ?? sequencer allows up to eight sources to be automatically scanned using one of four channel characteristic profiles without soft ware intervention. ?? eight-word conversion data fifo for dma operations. ?? includes two internal references (1.65 v fast-settling, 1.2/2.4 v precision), support for an external reference, and support for an external signal ground. 4.8.2. 10-bit digital-to-analog converter (idac0) the idac0 module takes a digital value as an input and outputs a proportional constant current on a pin. the idac0 module includes the following features: ?? 10-bit current dac with support for four timer, up to seven external i/o and on demand output update triggers. ?? ability to update on risi ng, falling, or both edges for any of the external i/o trigger sources. ?? supports an output update rate greater than 600 k samples per second. ?? support for three full-scale output mo des: 0.5 ma, 1.0 ma and 2.0 ma. ?? four-word fifo to aid with high-speed waveform generation or dma interactions. ?? individual fifo overrun, underrun, and went-empty interrupt status sources. ?? support for multiple data packing fo rmats, including: single 10-bit sample per word, dual 10-bit samples per word, or four 8-bi t samples per word. ?? support for left- and right-justified data. 4.8.3. low current comparators (cmp0, cmp1) the comparators take two analog input voltages and output the relationship between these voltages (less than or greater than) as a digital signal. the low power comparator (cmpn) module includes the following features: ?? multiple sources for the positive and negative inputs, including vbat, vref, and 8 i/o pins. ?? two outputs available: a digital synchronous latc hed output and a digital asynchronous raw output. ?? programmable hysteresis and response time. ?? falling or rising edge interrupt opt ions on the co mparator output. ?? 6-bit programmable reference divider. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 49 4.9. reset sources reset circuitry allows the sim3l1xx device to be easily pl aced in a predefined default condition. on entry to this reset state, th e following occur: ?? the core halts program execution. ?? module registers are initialized to their defined reset values unless the bits reset only with a power-on reset. ?? external port pins are forced to a known state. ?? interrupts and timers are disabled. ?? clocks to all ahb and apb peripherals revert to their reset state. all registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. the contents of ram are unaffected during a reset; any previously stored data is preserved as long as power is not lost. the port i/o latches are reset to 1 in open-drain mode. weak pullups are enabled during and after the reset. for vbat supply monitor and po wer-on resets, the reset pin is driven low until the device exits the reset state, allowing the reset pin to reset external devices. on exit from the reset state, the prog ram counter (pc) is reset, and the system clock defaults to the lposc0 clock output. the watchdog ti mer is enabled with the low frequency oscillator as its cl ock source. program execution begins at location 0x00000000. the reset sources can also optionally reset individual modules, including the low power mode charge pump, uart0, lcd0, advanced captur e counter (acctr0), and rtc0. figure 4.4. sim3l1xx reset sources block diagram reset sources reset vdd supply monitor missing clock detector watchdog timer software reset comparator 0 comparator 1 low power mode charge pump rtc0 alarm pmu pin wake core reset system or module reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 50 rev 0.4 4.10. security the peripherals on the sim3l1xx devices have a regist er lock and key mechanism that prevents undesired accesses of the peripherals from firmware. each bit in th e periphlockx registers contro ls a set of peripherals. a key sequence must be written to the key register to modify bits in perip hlockx. any subseq uent write to key will then inhibit accesses of periphlockx until it is unlocked again th rough key. reading the key register indicates the current status of the periphlockx lock state. figure 4.5. sim3l1xx security block diagram 4.11. on-chip debugging the sim3l1xx devices include jtag and serial wire programming and debugging interfaces and etm for instruction trace. the jtag interface is supported on sim3l1x7 devices only, and does not include boundary scan capabilites. the etm in terface is supported on sim3l1x7, and sim3l1x6 devices only . the jtag and etm interfaces can be optionally enabled to provide more visibility wh ile debugging at the cost of usin g several port i/o pins. additionally, if the core is configured for serial wi re (sw) mode and not jtag, then the serial wire viewer (swv) is available to provide a single pin to send out tp iu messages. serial wire viewer is supported on all sim3lxxx devices. most peripherals on sim3l1xx devices have the option to ha lt or continue functioning when the core halts in debug mode. peripheral lock and key i2c0 epca0 timer0/1 spi0/1 usart0, uart0 saradc0 cmp0/1 key periphlock0 periphlock1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 51 5. ordering information figure 5.1. sim3l1xx part numbering all devices in the sim3l1xx family have the following features: ?? core: arm cortex-m3 with maximum operating frequency of 50 mhz. ?? pll. ?? 10-channel dma controller. ?? 128/192/256-bit aes. ?? 16/32-bit crc. ?? encoder/decoder. ?? dc-dc buck converter. ?? timers: 3 x 32-bit (6 x 16-bit). ?? real-time clock. ?? low-power timer. ?? pca: 1 x 6 channels (enhanced) ?? adc: 12-bit 250 ksps (10-bit 1 msps) sar. ?? dac: 10-bit idac. ?? temperature sensor. ?? internal vref. ?? comparator: 2 x low current. ?? serial buses: 2 x usart, 2 x spi, 1 x i2c additionally, all devices in the sim3l1 xx family include the low power mode advanced capture counter (acctr0), though the smaller packages (sim3l1x4) only support some of the external inputs and outputs. si m3 l 1 4 4 ? b gm ? silicon labs core ? m3 (cortex m3) family ? l (low power) feature set ? varies by family flash size ? 3 (32 kb), 4 (64 kb), 5 (128 kb), 6 (256 kb) pin count ? 4 (40 pin), 6 (64 pin), 7 (80 pin) revision temperature grade and package type www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 52 rev 0.4 table 5.1. product selection guide ordering part number flash memory (kb) ram (kb) lcd segments digital port i/os digital port i/os on the crossbar number of saradc0 channels number of comparator 0/1 inputs (+/-) number of pmu pin wake sources number of acctr0 inputs and outputs jtag debugging interface etm debugging interface serial wire debugging interface lead-free (rohs compliant) package sim3l167-c-gq 256 32 160 (4x40) 62 38 24 15/15 14 12 ? ? ? ? tqfp-80 sim3l167-c-gl 256 32 160 (4x40) 62 38 24 15/15 14 12 ? ? ? ? tfbga-80 sim3l166-c-gm 256 32 128 (4x32) 51 34 23 14/12 11 12 ? ? ? qfn-64 sim3l166-c-gq 256 32 128 (4x32) 51 34 23 14/12 11 12 ? ? ? tqfp-64 sim3l164-c-gm 256 32 28 26 20 9/10 11 5 ? ? qfn-40 sim3l157-c-gq 128 32 160 (4x40) 62 38 24 15/15 14 12 ? ? ? ? tqfp-80 sim3l157-c-gl 128 32 160 (4x40) 62 38 24 15/15 14 12 ? ? ? ? tfbga-80 sim3l156-c-gm 128 32 128 (4x32) 51 34 23 14/12 11 12 ? ? ? qfn-64 sim3l156-c-gq 128 32 128 (4x32) 51 34 23 14/12 11 12 ? ? ? tqfp-64 sim3l154-c-gm 128 32 28 26 20 9/10 11 5 ? ? qfn-40 sim3l146-c-gm 64 16 128 (4x32) 51 34 23 14/12 11 12 ? ? ? qfn-64 sim3l146-c-gq 64 16 128 (4x32) 51 34 23 14/12 11 12 ? ? ? tqfp-64 sim3l144-c-gm 64 16 28 26 20 9/10 11 5 ? ? qfn-40 sim3l136-c-gm 32 8 128 (4x32) 51 34 23 14/12 11 12 ? ? ? qfn-64 SIM3L136-C-GQ 32 8 128 (4x32) 51 34 23 14/12 11 12 ? ? ? tqfp-64 sim3l134-c-gm 32 8 28 26 20 9/10 11 5 ? ? qfn-40 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 53 6. pin definitions 6.1. sim3l1x7 pin definitions figure 6.1. sim3l1x7-gq pinout pb0.3 pb0.2 pb0.1 pb0.0 tms / swdio tck / swclk vio viorf vdrv vbat / vbatdc ind vss / vssdc vdc pb4.15 / traceclk pb4.14 / etm0 pb4.13 / etm1 pb4.12 / etm2 pb4.11 / etm3 pb4.10 pb4.9 pb4.8 pb4.7 pb4.6 pb4.5 pb4.4 pb4.3 pb4.2 pb4.1 pb4.0 vio vss pb3.15 pb3.14 pb3.13 pb3.12 pb3.11 pb3.10 pb3.9 pb3.8 pb3.7 pb1.6 / tdi pb1.7 pb1.8 pb1.9 pb1.10 pb1.11 pb2.0 pb2.1 vss pb2.4 pb2.5 pb2.6 pb2.7 pb3.0 pb3.1 pb3.2 pb3.3 pb3.4 pb3.5 pb3.6 pb0.4 pb0.5 pb0.6 pb0.7 pb0.8 pb0.9 pb0.10 pb0.11 / tdo / swv reset vss rtc1 rtc2 vio vlcd pb1.0 pb1.1 pb1.2 pb1.3 pb1.4 pb1.5 80-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 54 rev 0.4 figure 6.2. sim3l1x7-gl pinout pb0.3 pb0.5 pb0.7 pb0.9 pb0.11 / tdo / swv vlcd pb1.1 pb1.3 pb1.5 pb1.6 / tdi pb0.2 pb0.4 pb0.6 pb0.8 pb0.10 pb1.0 pb1.2 pb1.4 pb1.7 pb1.8 viorf pb0.1 reset rtc1 rtc2 vss pb1.9 pb1.10 vdrv pb0.0 vio vio pb1.11 pb2.0 vbat / vbatdc tck / swclk vss pb2.5 pb2.1 pb2.4 ind tms / swdio pb4.15 / traceclk pb2.6 pb3.1 pb2.7 vdc pb4.14 / etm0 vss / vssdc pb3.0 pb3.3 pb3.2 pb4.13 / etm1 pb4.11 / etm3 pb4.5 vss pb4.0 vio pb3.5 pb3.4 pb4.12 / etm2 pb4.9 pb4.7 pb4.4 pb4.2 pb3.14 pb3.12 pb3.10 pb3.7 pb3.6 pb4.10 pb4.8 pb4.6 pb4.3 pb4.1 pb3.15 pb3.13 pb3.11 pb3.9 pb3.8 80 pin tfbga (top view) 12 10 3456789 a k j h g f e d c b www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 55 table 6.1. pin definitions and alternate functions for sim3l1x7 pin name type pin numbers (tqfp-80) pin numbers (tfbga-80) i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions vss ground 12 31 52 71 c7 e3 g3 h5 vssdc ground (dc- dc) 12 g3 vio power (i/o) 7 30 68 d3 d8 h7 viorf power (rf i/o) 8 c1 vbat/ vbatdc 10 e1 vdrv 9 d1 vdc 13 g1 vlcd power (lcd charge pump) 67 a6 ind dc-dc inductor 11 f1 reset active-low reset 72 c4 tck/ swclk jtag / serial wire 6 e2 tms/ swdio jtag / serial wire 5 f2 rtc1 rtc oscillator input 70 c5 rtc2 rtc oscillator output 69 c6 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 56 rev 0.4 pb0.0 standard i/o 4 d2 vio ? ? ? int0.0 wake.0 adc0.20 vref cmp0p.0 pb0.1 standard i/o 3 c2 vio ? ? ? int0.1 wake.1 adc0.21 vrefgnd cmp0n.0 pb0.2 standard i/o 2 b1 vio ? ? ? int0.2 wake.2 adc0.22 cmp1p.0 xtal2 pb0.3 standard i/o 1 a1 vio ? ? ? int0.3 wake.3 adc0.23 cmp1n.0 xtal1 pb0.4 standard i/o 80 b2 vio ? ? ? int0.4 wake.4 adc0.0 cmp0p.1 idac0 pb0.5 standard i/o 79 a2 vio ? ? ? int0.5 wake.5 acctr0_stop0 acctr0_in0 pb0.6 standard i/o 78 b3 vio ? ? ? int0.6 wake.6 acctr0_stop1 acctr0_in1 pb0.7 standard i/o 77 a3 vio ? ? ? int0.7 wake.7 acctr0_lcin0 pb0.8 standard i/o 76 b4 vio ? ? ? lpt0t0 lpt0out0 int0.8 wake.8 acctr0_lcin1 table 6.1. pin definitions and alternate functions for sim3l1x7 (continued) pin name type pin numbers (tqfp-80) pin numbers (tfbga-80) i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 57 pb0.9 standard i/o 75 a4 vio ? ? ? lpt0t1 int0.9 wake.9 acctr0_lcpul0 adc0.1 cmp0n.1 pb0.10 standard i/o 74 b5 vio ? ? ? lpt0t2 int0.10 wake.10 acctr0_lcpul1 adc0.2 cmp1p.1 pb0.11/ tdo/swv standard i/o / jtag / serial wire viewer 73 a5 vio ? ? ? lpt0t3 lpt0out1 int0.11 wake.11 adc0.3 cmp1n.1 pb1.0 standard i/o 66 b6 vio ? ? lcd0.39 lpt0t4 int0.12 acctr0_lcbias0 cmp0p.2 pb1.1 standard i/o 65 a7 vio ? ? lcd0.38 lpt0t5 int0.13 acctr0_lcbias1 cmp0n.2 pb1.2 standard i/o 64 b7 vio ? ? lcd0.37 lpt0t6 int0.14 uart0_tx cmp1p.2 pb1.3 standard i/o 63 a8 vio ? ? lcd0.36 lpt0t7 int0.15 uart0_rx cmp1n.2 pb1.4 standard i/o 62 b8 vio ? ? lcd0.35 acctr0_dbg0 adc0.4 pb1.5 standard i/o 61 a9 vio ? ? lcd0.34 acctr0_dbg1 adc0.5 pb1.6/tdi standard i/o / jtag 60 a10 vio ? ? lcd0.33 adc0.6 pb1.7 standard i/o 59 b9 vio ? ? lcd0.32 rtc0tclk_out adc0.7 table 6.1. pin definitions and alternate functions for sim3l1x7 (continued) pin name type pin numbers (tqfp-80) pin numbers (tfbga-80) i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 58 rev 0.4 pb1.8 standard i/o 58 b10 vio ? ? lcd0.31 cmp0p.3 pb1.9 standard i/o 57 c9 vio ? ? lcd0.30 cmp0n.3 pb1.10 standard i/o 56 c10 vio ? ? lcd0.29 cmp1p.3 pb1.11 standard i/o 55 d9 vio ? ? lcd0.28 cmp1n.3 pb2.0 standard i/o 54 d10 viorf ? ? lpt0t8 int1.0 wake.12 spi1_cts adc0.8 cmp0p.4 pb2.1 standard i/o 53 e9 viorf ? ? lpt0t9 int1.1 wake.13 viorfclk adc0.9 cmp0n.4 pb2.4 standard i/o 51 e10 viorf ? ? lpt0t12 int1.4 spi1_sclk adc0.10 cmp0p.5 pb2.5 standard i/o 50 e8 viorf ? ? lpt0t13 int1.5 spi1_miso adc0.11 cmp0n.5 pb2.6 standard i/o 49 f8 viorf ? ? lpt0t14 int1.6 spi1_mosi adc0.12 cmp1p.5 pb2.7 standard i/o 48 f10 viorf ? ? int1.7 spi1_nss adc0.13 cmp1n.5 pb3.0 standard i/o 47 g8 vio ? ? lcd0.27 int1.8 adc0.14 pb3.1 standard i/o 46 f9 vio ? ? lcd0.26 int1.9 adc0.15 pb3.2 standard i/o 45 g10 vio ? ? lcd0.25 int1.10 adc0.16 pb3.3 standard i/o 44 g9 vio ? ? lcd0.24 int1.11 adc0.17 table 6.1. pin definitions and alternate functions for sim3l1x7 (continued) pin name type pin numbers (tqfp-80) pin numbers (tfbga-80) i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 59 pb3.4 standard i/o 43 h10 vio ? ? lcd0.23 int1.12 cmp0p.6 pb3.5 standard i/o 42 h9 vio ? ? lcd0.22 int1.13 cmp0n.6 pb3.6 standard i/o 41 j10 vio ? ? lcd0.21 int1.14 cmp1p.6 pb3.7 standard i/o 40 j9 vio ? ? lcd0.20 int1.15 cmp1n.6 pb3.8 standard i/o 39 k10 vio ? lcd0.19 cmp0p.7 pb3.9 standard i/o 38 k9 vio ? lcd0.18 cmp0n.7 pb3.10 standard i/o 37 j8 vio ? lcd0.17 cmp1p.7 pb3.11 standard i/o 36 k8 vio ? lcd0.16 cmp1n.7 pb3.12 standard i/o 35 j7 vio ? lcd0.15 adc0.18 pb3.13 standard i/o 34 k7 vio ? lcd0.14 adc0.19 pb3.14 standard i/o 33 j6 vio ? com0.3 pb3.15 standard i/o 32 k6 vio ? com0.2 pb4.0 standard i/o 29 h6 vio ? com0.1 pb4.1 standard i/o 28 k5 vio ? com0.0 pb4.2 standard i/o 27 j5 vio ? lcd0.13 pb4.3 standard i/o 26 k4 vio ? lcd0.12 pb4.4 standard i/o 25 j4 vio ? lcd0.11 pb4.5 standard i/o 24 h4 vio ? lcd0.10 pb4.6 standard i/o 23 k3 vio ? lcd0.9 pmu_asleep pb4.7 standard i/o 22 j3 vio ? lcd0.8 pb4.8 standard i/o 21 k2 vio ? lcd0.7 table 6.1. pin definitions and alternate functions for sim3l1x7 (continued) pin name type pin numbers (tqfp-80) pin numbers (tfbga-80) i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 60 rev 0.4 pb4.9 standard i/o 20 j2 vio ? lcd0.6 pb4.10 standard i/o 19 k1 vio ? lcd0.5 pb4.11/ etm3 standard i/o / etm 18 h2 vio ? lcd0.4 pb4.12/ etm2 standard i/o / etm 17 j1 vio ? lcd0.3 pb4.13/ etm1 standard i/o / etm 16 h1 vio ? lcd0.2 pb4.14/ etm0 standard i/o / etm 15 g2 vio ? lcd0.1 pb4.15/ trace - clk standard i/o / etm 14 f3 vio ? lcd0.0 table 6.1. pin definitions and alternate functions for sim3l1x7 (continued) pin name type pin numbers (tqfp-80) pin numbers (tfbga-80) i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 61 6.2. sim3l1x6 pin definitions figure 6.3. sim3l1x6-gq pinout pb0.2 pb0.1 pb0.0 tms / swdio tck / swclk vio viorf / vdrv vbat / vbatdc ind vss / vssdc vdc pb4.12 / traceclk pb4.11 / etm0 pb4.10 / etm1 pb4.9 / etm2 pb4.8 / etm3 pb4.7 pb4.6 pb4.5 pb4.4 pb4.3 pb4.2 pb4.1 pb4.0 pb3.11 pb3.10 pb3.9 pb3.8 pb3.7 pb3.6 pb3.5 pb3.4 pb1.5 pb1.6 pb1.7 pb1.8 pb1.9 pb1.10 pb2.0 vss pb2.4 pb2.5 pb2.6 pb2.7 pb3.0 pb3.1 pb3.2 pb3.3 pb0.3 pb0.4 pb0.5 pb0.6 pb0.7 pb0.8 pb0.9 / swv reset rtc1 rtc2 vlcd pb1.0 pb1.1 pb1.2 pb1.3 pb1.4 64 pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 62 rev 0.4 figure 6.4. sim3l1x6-gm pinout pb0.2 pb0.1 pb0.0 tms / swdio tck / swclk vio viorf / vdrv vbat / vbatdc ind vss / vssdc vdc pb4.12 / traceclk pb4.11 / etm0 pb4.10 / etm1 pb4.9 / etm2 pb4.8 / etm3 pb4.7 pb4.6 pb4.5 pb4.4 pb4.3 pb4.2 pb4.1 pb4.0 pb3.11 pb3.10 pb3.9 pb3.8 pb3.7 pb3.6 pb3.5 pb3.4 pb1.5 pb1.6 pb1.7 pb1.8 pb1.9 pb1.10 pb2.0 vss pb2.4 pb2.5 pb2.6 pb2.7 pb3.0 pb3.1 pb3.2 pb3.3 pb0.3 pb0.4 pb0.5 pb0.6 pb0.7 pb0.8 pb0.9 / swv reset rtc1 rtc2 vlcd pb1.0 pb1.1 pb1.2 pb1.3 pb1.4 58 49 64 63 62 61 60 59 57 56 52 55 54 53 51 50 42 33 48 47 46 45 44 43 41 40 36 39 38 37 35 34 8 1 2 3 4 5 6 7 9 10 14 11 12 13 15 16 24 17 18 19 20 21 22 23 25 26 30 27 28 29 31 32 64 pin qfn (topview) vss www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 63 table 6.2. pin definitions and alternate functions for sim3l1x6 pin name type pin numbers i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions vss ground 10 41 vssdc ground (dc-dc) 10 vio power (i/o) 6 viorf / vdrv power (rf i/o) 7 vbat / vbatdc 8 vdc 11 vlcd power (lcd charge pump) 54 ind dc-dc inductor 9 reset active-low reset 57 tck/ swclk jtag / serial wire 5 tms/ swdio jtag / serial wire 4 rtc1 rtc oscillator input 56 rtc2 rtc oscillator output 55 pb0.0 standard i/o 3 vio xbr 0 ? ? int0.0 wake.0 adc0.20 vref cmp0p.0 pb0.1 standard i/o 2 vio xbr 0 ? ? int0.1 wake.2 adc0.22 cmp0n.0 cmp1p.0 xtal2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 64 rev 0.4 pb0.2 standard i/o 1 vio xbr 0 ? ? int0.2 wake.3 adc0.23 cmp1n.0 xtal1 pb0.3 standard i/o 64 vio xbr 0 ? ? int0.3 wake.4 adc0.0 cmp0p.1 idac0 pb0.4 standard i/o 63 vio xbr 0 ? ? int0.4 wake.5 acctr0_stop0 acctr0_in0 pb0.5 standard i/o 62 vio xbr 0 ? ? int0.5 wake.6 acctr0_stop1 acctr0_in1 pb0.6 standard i/o 61 vio xbr 0 ? ? int0.6 wake.7 acctr0_lcin0 pb0.7 standard i/o 60 vio xbr 0 ? ? lpt0t0 lpt0out0 int0.7 wake.8 acctr0_lcin1 pb0.8 standard i/o 59 vio xbr 0 ? ? lpt0t1 int0.8 wake.9 acctr0_lcpul0 adc0.1 cmp0n.1 pb0.9/swv standard i/o /serial wire viewer 58 vio xbr 0 ? ? lpt0t2 int0.9 wake.10 lpt0out1 adc0.2 cmp1p.1 pb1.0 standard i/o 53 vio xbr 0 ? lcd0.31 lpt0t4 int0.12 acctr0_lcbias0 cmp0p.2 table 6.2. pin definitions and alternate functions for sim3l1x6 (continued) pin name type pin numbers i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 65 pb1.1 standard i/o 52 vio xbr 0 ? lcd0.30 lpt0t5 int0.13 acctr0_lcbias1 cmp0n.2 pb1.2 standard i/o 51 vio xbr 0 ? lcd0.29 lpt0t6 int0.14 uart0_tx cmp1p.2 pb1.3 standard i/o 50 vio xbr 0 ? lcd0.28 lpt0t7 int0.15 uart0_rx cmp1n.2 pb1.4 standard i/o 49 vio xbr 0 ? lcd0.27 acctr0_dbg0 adc0.3 pb1.5 standard i/o 48 vio xbr 0 ? lcd0.26 acctr0_dbg1 adc0.4 pb1.6 standard i/o 47 vio xbr 0 ? lcd0.25 rtc0tclk_out adc0.5 pb1.7 standard i/o 46 vio xbr 0 ? lcd0.24 cmp0p.3 pb1.8 standard i/o 45 vio xbr 0 ? lcd0.23 cmp0n.3 pb1.9 standard i/o 44 vio xbr 0 ? lcd0.22 cmp1p.3 pb1.10 standard i/o 43 vio xbr 0 ? lcd0.21 cmp1n.3 pb2.0 standard i/o 42 vior f xbr 0 ? lpt0t8 int1.0 wake.12 spi1_cts adc0.6 cmp0p.4 pb2.4 standard i/o 40 vior f xbr 0 ? lpt0t12 int1.4 spi1_sclk adc0.7 cmp0p.5 table 6.2. pin definitions and alternate functions for sim3l1x6 (continued) pin name type pin numbers i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 66 rev 0.4 pb2.5 standard i/o 39 vior f xbr 0 ? lpt0t13 int1.5 spi1_miso adc0.8 cmp0n.5 pb2.6 standard i/o 38 vior f xbr 0 ? lpt0t14 int1.6 spi1_mosi adc0.9 cmp1p.5 pb2.7 standard i/o 37 vior f xbr 0 ? int1.7 spi1_nss adc0.10 cmp1n.5 pb3.0 standard i/o 36 vio xbr 0 ? lcd0.20 int1.8 adc0.11 pb3.1 standard i/o 35 vio xbr 0 ? lcd0.19 int1.9 adc0.12 pb3.2 standard i/o 34 vio xbr 0 ? lcd0.18 int1.10 cmp0p.6 pb3.3 standard i/o 33 vio xbr 0 ? lcd0.17 int1.11 cmp0n.6 pb3.4 standard i/o 32 vio xbr 0 ? lcd0.16 int1.12 cmp0p.7 pb3.5 standard i/o 31 vio xbr 0 ? lcd0.15 int1.13 cmp0n.7 pb3.6 standard i/o 30 vio xbr 0 ? lcd0.14 int1.14 cmp1p.7 pb3.7 standard i/o 29 vio xbr 0 ? lcd0.13 int1.15 cmp1n.7 pb3.8 standard i/o 28 vio ? lcd0.12 adc0.13 pb3.9 standard i/o 27 vio ? lcd0.11 adc0.14 pb3.10 standard i/o 26 vio ? com0.3 pb3.11 standard i/o 25 vio ? com0.2 table 6.2. pin definitions and alternate functions for sim3l1x6 (continued) pin name type pin numbers i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 67 pb4.0 standard i/o 24 vio ? com0.1 pb4.1 standard i/o 23 vio ? com0.0 pb4.2 standard i/o 22 vio ? lcd0.10 adc0.19 pb4.3 standard i/o 21 vio ? lcd0.9 pb4.4 standard i/o 20 vio ? lcd0.8 pb4.5 standard i/o 19 vio ? lcd0.7 pb4.6 standard i/o 18 vio ? lcd0.6 pmu_asleep pb4.7 standard i/o 17 vio ? lcd0.5 pb4.8/etm3 standard i/o / etm 16 vio ? lcd0.4 pb4.9/etm2 standard i/o / etm 15 vio ? lcd0.3 pb4.10/ etm1 standard i/o / etm 14 vio ? lcd0.2 pb4.11/ etm0 standard i/o / etm 13 vio ? lcd0.1 pb4.12/ traceclk standard i/o / etm 12 vio ? lcd0.0 table 6.2. pin definitions and alternate functions for sim3l1x6 (continued) pin name type pin numbers i/o voltage domain crossbar capability port match lcd interface output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 68 rev 0.4 6.3. sim3l1x4 pin definitions figure 6.5. sim3l1x4-gm pinout 23 33 18 8 40 39 38 37 36 35 34 1 2 3 4 5 6 7 11 12 13 14 15 16 17 30 29 28 27 26 25 24 32 31 20 19 10 9 21 22 40 pin qfn (top view) pb0.1 pb0.0 tms / swdio tck / swclk vio viorf / vdrv vbat / vbatdc ind vss / vssdc vdc pb3.9 pb3.8 pb3.7 pb3.6 pb3.5 pb3.4 pb3.3 pb3.2 pb3.1 pb3.0 pb0.9 pb2.0 pb2.1 pb2.2 pb2.3 vss pb2.4 pb2.5 pb2.6 pb2.7 pb0.2 pb0.3 pb0.4 pb0.5 pb0.6 / swv reset rtc1 rtc2 pb0.7 pb0.8 vss www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 69 table 6.3. pin definitions and alternate functions for sim3l1x4 pin name type pin numbers i/o voltage domain crossbar capability port match output toggle logic external trigger inputs / digital functions analog functions vss ground 9 25 vssdc ground (dc-dc) 9 vio power (i/o) 5 viorf / vdrv power (rf i/o) 6 vbat / vbatdc 7 vdc 10 ind dc-dc inductor 8 reset active-low reset 35 tck/swclk jtag/serial wire 4 tms/swdio jtag/serial wire 3 rtc1 rtc oscillator input 34 rtc2 rtc oscillator output 33 pb0.0 standard i/o 2 vio xbr0 ? ? int0.0 wake.0 adc0.20 vref cmp0p.0 pb0.1 standard i/o 1 vio xbr0 ? ? int0.1 wake.2 adc0.22 cmp0n.0 cmp1p.0 xtal2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 70 rev 0.4 pb0.2 standard i/o 40 vio xbr0 ? ? int0.2 wake.3 adc0.23 cmp0n.1 cmp1n.0 xtal1 pb0.3 standard i/o 39 vio xbr0 ? ? int0.3 wake.4 adc0.0 cmp0p.1 idac0 pb0.4 standard i/o 38 vio xbr0 ? ? int0.4 wake.5 acctr0_stop0 acctr0_in0 pb0.5 standard i/o 37 vio xbr0 ? ? int0.5 wake.6 acctr0_stop1 acctr0_in1 pb0.6/swv standard i/o /serial wire viewer 36 vio xbr0 ? ? lpt0t0 lpt0out0 int0.6 wake.8 acctr0_lcin1 pb0.7 standard i/o 32 vio xbr0 ? ? lpt0t6 int0.7 uart0_tx cmp1p.2 pb0.8 standard i/o 31 vio xbr0 ? ? lpt0t7 int0.8 uart0_rx cmp1n.2 pb0.9 standard i/o 30 vio xbr0 ? ? lpt0t1 int0.9 rtc0tclk_out adc0.1 pb2.0 standard i/o 29 viorf xbr0 ? lpt0t8 int1.0 wake.12 spi1_cts adc0.2 cmp0p.4 table 6.3. pin definitions and alternate functions for sim3l1x4 (continued) pin name type pin numbers i/o voltage domain crossbar capability port match output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 71 pb2.1 standard i/o 28 viorf xbr0 ? lpt0t9 int1.1 wake.13 viorfclk adc0.3 cmp0n.4 pb2.2 standard i/o 27 viorf xbr0 ? lpt0t10 int1.2 wake.14 adc0.4 cmp1p.4 pb2.3 standard i/o 26 viorf xbr0 ? lpt0t11 int1.3 wake.15 adc0.5 cmp1n.4 pb2.4 standard i/o 24 viorf xbr0 ? lpt0t12 int1.4 spi1_sclk adc0.6 cmp0p.5 pb2.5 standard i/o 23 viorf xbr0 ? lpt0t13 int1.5 spi1_miso adc0.7 cmp0n.5 pb2.6 standard i/o 22 viorf xbr0 ? lpt0t14 int1.6 spi1_mosi adc0.8 cmp1p.5 pb2.7 standard i/o 21 viorf xbr0 ? int1.7 spi1_nss adc0.9 cmp1n.5 pb3.0 standard i/o 20 vio xbr0 ? int1.8 cmp0n.7 pb3.1 standard i/o 19 vio xbr0 ? int1.9 cmp1p.7 pb3.2 standard i/o 18 vio xbr0 ? int1.10 cmp1n.7 pb3.3 standard i/o 17 vio xbr0 ? int1.11 adc0.10 pb3.4 standard i/o 16 vio xbr0 ? int1.12 adc0.11 pb3.5 standard i/o 15 vio xbr0 ? int1.13 adc0.12 table 6.3. pin definitions and alternate functions for sim3l1x4 (continued) pin name type pin numbers i/o voltage domain crossbar capability port match output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 72 rev 0.4 pb3.6 standard i/o 14 vio xbr0 ? int1.14 adc0.13 pb3.7 standard i/o 13 vio xbr0 ? int1.15 adc0.14 pb3.8 standard i/o 12 vio ? adc0.15 pb3.9 standard i/o 11 vio ? adc0.16 table 6.3. pin definitions and alternate functions for sim3l1x4 (continued) pin name type pin numbers i/o voltage domain crossbar capability port match output toggle logic external trigger inputs / digital functions analog functions www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 73 6.4. tqfp-80 pa ckage specifications figure 6.6. tqfp-80 package drawing www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 74 rev 0.4 table 6.4. tqfp-80 package dimensions dimension min nominal max a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 b 0.17 0.20 0.27 c 0.09 ? 0.20 d 14.00 bsc d1 12.00 bsc e 0.50 bsc e 14.00 bsc e1 12.00 bsc l 0.45 0.60 0.75 l1 1.00 ref ? 0 3.5 7 aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec ms-026, variant add. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 75 figure 6.7. tqfp-80 landing diagram table 6.5. tqfp-80 landing diagram dimensions dimension min max c1 13.30 13.40 c2 13.30 13.40 e 0.50 bsc x 0.20 0.30 y 1.40 1.50 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 76 rev 0.4 6.4.1. tqfp-80 solder mask design all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 6.4.2. tqfp-80 stencil design 1. a stainless steel, laser-cut and electro-polished st encil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all pads. 6.4.3. tqfp-80 card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 spec ification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 77 6.5. tfbga-80 package specifications figure 6.8. tfbga-80 package drawing ? e d1 e1 ?b d e c a1 a2 a www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 78 rev 0.4 table 6.6. tfbga-80 package dimensions dimension min nominal max a ? ? 1.20 a1 0.16 0.21 0.26 a2 0.84 0.89 0.94 b 0.25 0.30 0.35 c 0.32 0.36 0.40 d 5.40 5.50 5.60 e 5.40 5.50 5.60 e1 ? 4.50 ? d1 ? 4.50 ? e ? 0.50 ? aaa 0.15 bbb 0.10 ddd 0.08 eee 0.15 fff 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 79 figure 6.9. tfbga-80 landing diagram table 6.7. tfbga-80 landing diagram dimensions dimension min nom max x 0.25 0.30 0.35 c1 4.50 c2 4.50 e1 0.50 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per th e ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. ? c2 c1 e1 x www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 80 rev 0.4 6.5.1. tfbga-80 solder mask design all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 6.5.2. tfbga-80 stencil design 1. a stainless steel, laser-cut and electro-polished st encil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1. 6.5.3. tfbga-80 card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 spec ification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 81 6.6. qfn-64 package specifications figure 6.10. qfn-64 package drawing table 6.8. qfn-64 package dimensions dimension min nominal max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 9.00 bsc d2 3.95 4.10 4.25 e 0.50 bsc e 9.00 bsc e2 3.95 4.10 4.25 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 82 rev 0.4 figure 6.11. qfn-64 landing diagram table 6.9. qfn-64 landing diagram dimensions dimension mm c1 8.90 c2 8.90 e 0.50 x1 0.30 y1 0.85 x2 4.25 y2 4.25 notes: 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 83 6.6.1. qfn-64 solder mask design all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 6.6.2. qfn-64 stencil design 1. a stainless steel, laser-cut and electro-polished st encil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. a 3x3 array of 1.0 mm square openings on a 1. 5 mm pitch should be used for the center ground pad. 6.6.3. qfn-64 card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 spec ification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 84 rev 0.4 6.7. tqfp-64 pa ckage specifications figure 6.12. tqfp-64 package drawing www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 85 table 6.10. tqfp-64 package dimensions dimension min nominal max a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 ? 0.20 d 12.00 bsc d1 10.00 bsc e 0.50 bsc e 12.00 bsc e1 10.00 bsc l 0.45 0.60 0.75 ? 0 3.5 7 aaa ? ? 0.20 bbb ? ? 0.20 ccc ? ? 0.08 ddd ? ? 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec ms-026, variant acd. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 86 rev 0.4 figure 6.13. tqfp-64 landing diagram table 6.11. tqfp-64 landing diagram dimensions dimension min max c1 11.30 11.40 c2 11.30 11.40 e 0.50 bsc x 0.20 0.30 y 1.40 1.50 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 87 6.7.1. tqfp-64 solder mask design all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 6.7.2. tqfp-64 stencil design 1. a stainless steel, laser-cut and electro-polished st encil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all pads. 6.7.3. tqfp-64 card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 spec ification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 88 rev 0.4 6.8. qfn-40 package specifications figure 6.14. qfn-40 package drawing table 6.12. qfn-40 package dimensions dimension min nominal max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 6.00 bsc d2 4.35 4.50 4.65 e 0.50 bsc e 6.00 bsc e2 4.35 4.5 4.65 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 89 figure 6.15. qfn-40 landing diagram table 6.13. qfn-40 landing diagram dimensions dimension mm c1 5.90 c2 5.90 e 0.50 x1 0.30 y1 0.85 x2 4.65 y2 4.65 notes: 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 90 rev 0.4 6.8.1. qfn-40 solder mask design all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 6.8.2. qfn-40 stencil design 1. a stainless steel, laser-cut and electro-polished st encil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. a 3x3 array of 1.1 mm square openings on a 1. 6 mm pitch should be used for the center ground pad. 6.8.3. qfn-40 card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 spec ification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 91 7. revision specific behavior this chapter describes any differences between released revisions of the device. 7.1. revision identification the lot id code on the top side of the device package can be used for decoding device revision information. figures 7.1, 7.2, and 7.3 show how to find the lo t id code on the top side of the device package. in addition, firmware can determine the revision of the device by checking the deviceid registers. figure 7.1. sim3l1x7-gq revision information figure 7.2. sim3l1x6-gm and sim3l1x6-gq revision information these characters identify the device revision sim3l167 c -gq 1221 c cs701 tw e3 these characters identify the device revision sim3l166 c -gm 1221 c cs701 tw e3 sim3l166 c -gq 1221 c cs701 tw e3 qfn-64 tqfp-64 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 92 rev 0.4 figure 7.3. sim3l1x7-gl and sim3l1x4-gm revision information sim3l 164 c cs701 1221 this character identifies the device revision sim3l 167 c cs701 1221 tfbga-80 qfn-40 www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx rev 0.4 93 n otes : www.datasheet.net/ datasheet pdf - http://www..co.kr/
sim3l1xx 94 rev 0.4 c ontact i nformation silicon laboratories inc. 400 west cesar chavez ? austin, tx 78701 please visit the silicon labs technical support web page: ? https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ? and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive pat ent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibili ty for errors and omissions, and disclaim s responsibility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding t he suitability of its products for any par ticular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages. www.datasheet.net/ datasheet pdf - http://www..co.kr/

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